Semiconductor structure with back-gate switching
AssigneeGlobalfoundries Inc.
InventorsMichael Otto, Nigel Chan
Life of this patent
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Abstract
The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.
Claims9
A circuit comprising a plurality of pairs of MOS devices, each pair comprised of a first MOS device and a second MOS device, wherein each pair of MOS devices is coupled to at least one front-gate contact and two digital back-gate potentials each of which are separately connected to a single device of the first MOS device and the second MOS device, wherein each of the two digital back gate potentials provide separate logical function implementation on a back side of its corresponding single device, by each being switchable between two logic levels, and wherein the digital back-gate potentials for the logical function implementation include a first common contact connected to each first MOS device of the plurality of pairs of MOS devices and a second common contact connected to each second MOS device of the plurality of pairs of MOS devices such that each of the first MOS devices shares a physical back-gate control with other first MOS devices and each of the second MOS devices shares a physical back-gate control with other second MOS devices.
An operation of a logic back-gate control for separately controlling multiple devices, comprising each logic-back gate control for the multiple devices providing a logical low level (Vbg_off) and a logical high level (Vbg_on) to a back-gate of each of the multiple devices, wherein the multiple devices comprise a plurality of pairs of MOS devices, each pair comprised of a first MOS device and a second MOS device, and wherein the logic-back gate control providing a logical low level (Vbg_off) and a logical high level (Vbg_on) to a back-gate of each of the multiple devices includes a first common contact connected to each first MOS device of the plurality of pairs of MOS devices and a second common contact connected to each second MOS device of the plurality of pairs of MOS devices such that each of the first MOS devices shares a physical back-gate control with other first MOS devices and each of the second MOS devices shares a physical back-gate control with other second MOS devices.
Dependencies are inferred from the claim text.