Piezoelectric and logic integrated delay line memory

A delay line memory chip device, comprising:

• a substrate;
• and
• a first acoustic communication unit and a second acoustic communication unit disposed on a first side and a second side of the substrate, respectively, wherein the first and second acoustic communication units each include an electronic component coupled between a transmit piezoelectric transducer and a receive piezoelectric transducer,
• wherein the electronic unit of the first acoustic communication unit is operable to receive, amplify, and/or synchronize data signals into a bit stream to be transmitted as acoustic pulses carrying data stored in the delay line memory device,
• wherein the transmit piezoelectric transducer of the first communication unit is operable to transduce and transmit the bit stream of the data signals received from the electronic unit of the first acoustic communication unit to the acoustic pulses that carry the data through a first portion in the bulk of the substrate to be received by the receive piezoelectric transducer of the second communication unit, wherein the receive piezoelectric transducer of the second transducer is operable to transduce the received acoustic pulses to intermediate signals containing the data,
• wherein the electronic unit of the second acoustic communication unit is operable to receive and amplify the intermediate signals to be transmitted as return acoustic pulses carrying the data to the first acoustic communication unit,
• wherein the transmit piezoelectric transducer of the second communication unit is operable to transduce and transmit the intermediate signals received from the electronic unit of the second acoustic communication unit to the return acoustic pulses that contain the data through a second portion in the bulk of the substrate to be received by the receive piezoelectric transducer of the first communication unit.

A method to store data in a delay line memory, comprising:

• receiving, at an electronics unit of the delay line memory, data signals from an integrated circuit device, wherein the data signals include bits of data;
• transducing, at a first piezoelectric transducer of the delay line memory, the data signals into acoustic pulses carrying the bits of data;
• transmitting, through a bulk material of the delay line memory, the acoustic pulses to a second piezoelectric transducer of the delay line memory;
• transducing, at the second piezoelectric transducer, the acoustic pulses to intermediate electrical signals containing the data to be received by a second electronic unit of the delay line memory;
• and
• transferring the intermediate electrical signals through an electrical interconnect coupled from the second electronic unit to the electronic unit.

A delay line memory device, comprising:

• a substrate;
• an electronic unit disposed on a first side of the substrate, wherein the electronic unit is operable to receive, amplify, and/or synchronize data signals into a bit stream to be transmitted as acoustic pulses carrying data stored in the delay line memory device;
• a first piezoelectric transducer and a second piezoelectric transducer disposed on the first side and a second side of the substrate, respectively, and in communication with the electronic unit, wherein the first piezoelectric transducer is operable to transduce and transmit the bit stream of the data signals received from the electronic unit to the acoustic pulses that carry the data through the bulk of the substrate, and the second piezoelectric transducer is operable to receive and transduce the transmitted acoustic pulses to intermediate electrical signals containing the data to be received by the electronic unit;
• and
• an electrical interconnect that electrically connects the electronic unit and the second piezoelectric transducer to transfer the intermediate electrical signals containing the data from the second piezoelectric transducer to the electronic unit.