Low-power data acquisition system and sensor interface

A sensor interface comprising:

• an on-chip relaxation oscillator circuit configured to generate a first clock signal;
• a digital phase locked loop (PLL) configured to generate a second clock signal based on the first clock signal, wherein the second clock signal is synchronized to the first clock signal;
• a first analog interface that includes:
• a first photodiode configured to generate a first current signal based on a first optical signal, wherein the first optical signal is representative of a first sensor signal;
• a first amplifier configured to generate a second current signal based on the first current signal and a feedback current signal;
• and
• a first analog to digital converter (ADC) configured to operate based on the second clock signal and to generate a first digital signal based on the second current signal;
• and
• a current digital to analog converter (CDAC) configured to operate based on the second clock signal and to generate an updated feedback current signal based on the first digital signal, wherein the updated feedback current signal reduces noise sensitivity of the first amplifier;
• and
• a second analog interface that includes:
• a second photodiode configured to generate a third current signal based on a second optical signal, wherein the second optical signal is representative of a second sensor signal;
• a low noise amplifier (LNA) to generate a first differential signal based on the third current signal that is representative of the second sensor signal;
• an anti-aliasing filter configured to generate a second differential signal based on the first differential signal;
• another ADC configured to operate based on the second clock signal and to generate a second digital signal based on the second differential signal;
• and
• a processor configured to:
• process the first digital signal to estimate first sensor data within the first sensor signal;
• and
• process the second digital signal to estimate second sensor data within the second sensor signal.

A method for execution by a sensor device, the method comprising:

• generating a first clock signal using an on-chip relaxation oscillator circuit;
• generating a second clock signal using a digital phase locked loop (PLL) and based on the first clock signal, wherein the second clock signal is synchronized to the first clock signal;
• operating a photodiode configured to generate a first current signal based on an optical signal, wherein the optical signal is representative of a sensor signal;
• generating a second current signal using an amplifier that operates based on the first current signal and a feedback current signal;
• digitally sampling the second current signal using an analog to digital converter (ADC) that operates based on the second clock signal to generate a digital signal;
• operating a current digital to analog converter (CDAC) that operates based on the second clock signal to generate an updated feedback current signal based on the digital signal, wherein the updated feedback current signal reduces noise sensitivity of the amplifier;
• and
• processing the digital signal to estimate sensor data within the sensor signal.