Reduction of power consumption in a half-duplex transceiver

A method of reducing power consumption in a half-duplex transceiver, the method comprising:

• receiving at least one transceiver operating input from at least one of a physical layer (PHY) subsystem and a medium access control layer (MAC) subsystem of the half-duplex transceiver;
• generating a control signal based on the at least one transceiver operating input;
• and
• providing the control signal to a direct current to direct current (DC-DC) converter of the half-duplex transceiver to operate the DC-DC converter in one of a plurality of snooze control modes based on the control signal, the DC-DC converter comprising a switching circuit and a driving circuit to drive the switching circuit, DC-DC converter configured to provide power supply from a battery input to at least one element of a transmitter subsystem of the half-duplex transceiver,
• wherein the plurality of snooze control modes corresponds to a plurality of snooze duty cycles,
• wherein in each snooze control mode of the plurality of snooze control modes, the switching circuit and the driver circuit remain in an OFF-state based on a respective snooze duty cycle;
• and
• wherein the at least one transceiver operating input comprises at least one PHY input from the PHY subsystem of the half-duplex transceiver, the at least one PHY input comprising at least one of a packet detect signal, a packet length signal and a clear channel assessment indicator signal.

A half-duplex transceiver, comprising:

• a transceiver subsystem comprising a transmitter subsystem comprising a power amplifier, and a receiver subsystem;
• and
• a power management circuit comprising:
• a direct current to direct current (DC-DC) converter comprising a switching circuit and a driver circuit to drive the switching circuit, the DC-DC converter configured to provide power supply from a battery input to the power amplifier of the transmitter sub-system, and further configured to operate in a plurality of snooze control modes;
• and
• a snooze mode controller coupled to the DC-DC converter and configured to generate a control signal based on at least one transceiver operating input of the half-duplex transceiver, wherein the control signal causes the DC-DC converter to operate in one of the plurality of snooze control modes, the plurality of snooze control modes corresponding to a plurality of snooze duty cycles and wherein in each snooze control mode of the plurality of snooze control modes, the switching circuit and the driver circuit remain in an OFF-state based on a respective snooze duty cycle;
• wherein the half-duplex transceiver comprises a physical layer (PHY) subsystem and wherein the at least one transceiver operating input comprises at least one PHY input from the PHY subsystem of the half-duplex transceiver;
• and
• wherein the at least one PHY input comprises at least one of a packet detect signal, a packet length signal and a clear channel assessment indicator signal.