Method and system for enforcing multiple rate limits with limited on-chip buffering

A system comprising:

• at least one memory of a host computing device, the at least one memory storing:
• at least one transmission queue adapted to receive at least one packet from a virtual machine (VM);
• and
• a transmission look-up table;
• and
• at least one rate limited secondary output queue;
• and
• one or more processors of the host computing device in communication with the at least one memory, the one or more processors adapted to:
• classify the at least one packet based on at least one entry in a transmission flow look-up table;
• determine whether the at least one packet should be delayed or transmitted immediately;
• and
• in response to determining that the at least one packet should be delayed, re-queue the at least one packet on the at least one rate limited secondary output queue.

A non-transitory computer readable medium comprising instructions executable by one or more processors on a host computing device to:

• receive at least one packet on at least one transmission queue assigned to a virtual machine (VM);
• classify the at least one packet based on at least one entry in a transmission flow look-up table;
• determine whether the at least one packet should be delayed or transmitted immediately based on its classification;
• and
• in response to determining that the at least one packet should be delayed, re-queue the at least one packet on one of a plurality of rate limited secondary output queues.