High data rate multilevel clock recovery system

A digital receiver system, comprising:

• an amplifier circuit configured to amplify a received analog signal, wherein the analog signal comprises a stream of data symbols, wherein each data symbol comprises a plurality of symbol components, including at least a first symbol component and a second symbol component;
• an ADC (analog-to-digital converter) circuit configured to sample the analog signal in response to a sample clock signal and generate a digital signal comprising a sequence of digital data samples, wherein each digital data sample corresponds to one data symbol in the analog signal;
• a digital equalization system configured to filter the digital signal to remove intersymbol interference and recover the stream of data symbols;
• and
• a clock recovery system configured to process the digital signal and generate the sample clock signal which is applied to the ADC circuit, wherein the clock recovery system comprises:
• a FFE (feed forward equalizer) circuit configured to remove precursor ISI (intersymbol interference) from the digital data samples and output FFE equalized data samples;
• and
• a multi-stage postcursor ISI equalizer circuit configured to remove postcursor ISI from the FFE equalized data samples, the multi-stage postcursor ISI equalizer circuit comprising:
• a first stage comprising a DFE (decision feedback equalizer) circuit configured to receive a current FFE equalized data sample, and remove a first component of postcursor ISI from the current FFE equalized data sample based on a DFE tap value H1 to generate a current DFE equalized data sample, wherein the first component of postcursor ISI which is removed from the current FFE equalized data sample comprises postcursor ISI which arises from a first symbol component of a previous digital data sample;
• and
• a second stage comprising a DFFE (decision feedforward equalizer) circuit configured to receive the current DFE equalized data sample, and remove a second component of postcursor ISI from the current FFE equalized data sample based on the same DFE tap value H1 to generate a current DFFE equalized data sample, wherein the second component of postcursor ISI which is removed from the current FFE equalized data sample comprises postcursor ISI which arises from a second symbol component of the previous digital data sample.

A method, comprising:

• receiving an analog signal, wherein the analog signal comprises a stream of data symbols, wherein each data symbol comprises a plurality of symbol components, including at least a first symbol component and a second symbol component;
• converting the analog signal into a digital signal by sampling the analog signal using a sample clock signal to generate a sequence of digital data samples, wherein each digital data sample corresponds to one data symbol in the analog signal;
• equalizing the digital signal using a FFE (feed forward equalization) process to remove precursor ISI (intersymbol interference) from the digital data samples and generate FFE equalized data samples;
• and
• processing a current FFE equalized data sample using a multi-stage postcursor ISI equalizer circuit configured to remove postcursor ISI from the current FFE equalized data sample, wherein processing the current FFE equalized data sample comprises:
• equalizing the current FFE equalized data sample using a DFE (decision feedback equalization) process to remove a first component of postcursor ISI from the current FFE equalized data sample based on a DFE tap value H1 to generate a current DFE equalized data sample, wherein the first component of postcursor ISI which is removed from the current FFE equalized data sample comprises postcursor ISI which arises from a first symbol component of a previous digital data sample;
• and
• equalizing the current DFE equalized data sample using a DFFE (decision feedforward equalization) function to remove a second component of postcursor ISI from the current FFE equalized data sample based on the same DFE tap value H1 to generate a current DFFE equalized data sample, wherein the second component of postcursor ISI which is removed from the current FFE equalized data sample comprises postcursor ISI which arises from a second symbol component of the previous digital data sample.