Method, apparatus and system for security application for integrated circuit devices

A non-transitory computer readable program storage unit encoded with instructions that, when executed by a computer, perform a method comprising:

• receiving a signal to configure a security access protocol for a memory device;
• performing at least one of setting or resetting of at least a portion of memory cells of said memory device in response to said signal to configure;
• providing a voltage having a first magnitude for switching said memory cells, wherein said voltage is capable of switching each of said memory cells with a first probability;
• providing a first address signal for addressing said memory cells;
• receiving a first response signal in response to said first address signal, wherein said response signal comprises the respective states of said memory cells;
• correlating said first address signal and said first response signal for generating an access key for said security access protocol;
• providing a second address signal, said second address signal is a challenge signal for a physical unclonable function (PUF) implementation;
• receiving a second response signal, wherein said second response signal is responsive to said second address signal and said second response signal comprises data relating to the state of said at least portion of said memory cells;
• determining whether data provided by said second response signal matches said access key;
• and
• providing access to said memory device in response to a determination that said second response signal matches said access key.

An apparatus, comprising:

• an interface for receiving a signal to configure a restricted access protocol for an integrated circuit device;
• a processor operatively coupled to said interface, wherein said processor is adapted to:
• perform at least one of setting or resetting of at least a portion of memory cells of a memory portion of said integrated circuit in response to said signal to configure;
• apply a voltage having a first magnitude for switching said memory cells, wherein said voltage is capable of switching each of said memory cells with a first probability;
• provide an address signal for addressing said memory cells;
• receive a response signal in response to said address signal, wherein said response signal comprises the respective states of said memory cells;
• correlate said address signal and said response signal for generating an access key for said restricted access protocol;
• provide a second address signal, wherein said second address signal is a challenge signal for a physical unclonable function (PUF) implementation;
• receive a second response signal, wherein said second response signal is responsive to said second address signal and said second response signal comprises data relating to the state of said at least portion of said memory cells:
• and
• determine whether data provided by said second response signal matches said access key;
• and
• a memory controller adapted to associate said access key with said memory device for providing restricted access to said memory device and to provide access to said integrated circuit device based on said access key and in response to a determination that said second response signal matches said access key.