Key extraction during secure boot

An integrated circuit comprising:

• a first volatile memory circuit configured to generate a plurality of initial logical state values upon power ON, wherein the first volatile memory circuit is an insecure volatile memory circuit;
• a secure volatile memory circuit secured by a secure execution environment (SEE);
• and
• a processing circuit configured to execute a secure boot flow that controls access to the first volatile memory circuit to secure secret data from one or more insecure applications, the processing circuit communicatively coupled to the first volatile memory circuit and the secure volatile memory circuit, the processing circuit further configured to
• initialize a resource power management circuit coupled to the first volatile memory circuit, the resource power management circuit configured to power ON the first volatile memory circuit,
• derive the secret data, wherein the secret data includes the plurality of initial logical state values,
• store the secret data in the secure volatile memory circuit,
• clear the plurality of initial logical state values in the first volatile memory circuit so that the first volatile memory circuit no longer stores one or more of the plurality of initial logical state values,
• execute an algorithm at the SEE to extract a secret key based on the secret data, and
• store the secret key in the secure volatile memory circuit,
• wherein the first volatile memory circuit is configured to be reset exclusively by the resource power management circuit to prevent the one or more insecure applications from resetting the first volatile memory circuit and obtaining the plurality of initial logical state values, and wherein the resetting of the first volatile memory circuit causes the processing circuit to execute the secure boot flow of the integrated circuit, where the secure boot flow includes a primary boot loader, a first secondary boot loader, and a second secondary boot loader, and the secure boot flow establishes a chain of trust.

An integrated circuit comprising:

• means for initializing a resource power management circuit coupled to a first volatile memory circuit, wherein the resource power management circuit is configured to power ON the first volatile memory circuit to generate a plurality of initial logical state values, wherein the first volatile memory circuit is an insecure volatile memory circuit on the integrated circuit;
• means for deriving secret data, wherein the secret data includes the plurality of initial logical state values;
• means for storing the secret data in a secure volatile memory circuit, the secure volatile memory circuit secured by a secure execution environment (SEE);
• means for clearing the plurality of initial logical state values in the first volatile memory circuit so that the first volatile memory circuit no longer stores one or more of the plurality of initial logical state values;
• means for executing an algorithm at the SEE to extract a secret key based on the secret data;
• and
• means for storing the secret key in the secure volatile memory circuit,
• wherein the first volatile memory circuit is configured to be reset exclusively by the resource power management circuit to prevent one or more insecure applications from resetting the first volatile memory circuit and obtaining the plurality of initial logical state values, and wherein the resetting of the first volatile memory circuit causes the integrated circuit to execute a secure boot flow that controls access to the first volatile memory circuit to secure the secret data from the one or more insecure applications, where the secure boot flow includes a primary boot loader, a first secondary boot loader, and a second secondary boot loader, and the secure boot flow establishes a chain of trust.

A non-transitory computer-readable storage medium having one or more instructions for a secure boot flow of an integrated circuit stored thereon, which when executed by the integrated circuit, causes the integrated circuit to:

• initialize a resource power management circuit coupled to a first volatile memory circuit;
• power ON the first volatile memory circuit to generate a plurality of initial logical state values, wherein the first volatile memory circuit is powered ON by the resource power management circuit and wherein the first volatile memory circuit is an insecure volatile memory circuit on the integrated circuit;
• derive secret data, wherein the secret data includes the plurality of initial logical state values;
• store the secret data in a secure volatile memory circuit, the secure volatile memory circuit secured by a secure execution environment (SEE);
• clear the plurality of initial logical state values in the first volatile memory circuit so that the first volatile memory circuit no longer stores one or more of the plurality of initial logical state values;
• execute an algorithm at the SEE to extract a secret key based on the secret data;
• and
• store the secret key in the secure volatile memory circuit,
• wherein the first volatile memory circuit is configured to be reset exclusively by the resource power management circuit to prevent one or more insecure applications from resetting the first volatile memory circuit and obtaining the plurality of initial logical state values, and wherein the resetting of the first volatile memory circuit causes the integrated circuit to execute the secure boot flow to control access to the first volatile memory circuit to secure the secret data from the one or more insecure applications, where the secure boot flow includes a primary boot loader, a first secondary boot loader, and a second secondary boot loader, and the secure boot flow establishes a chain of trust.