Phase calibration of clock signals
AssigneeRambus Inc.
InventorsMarko Aleksić, Simon Li, Roxanne Vu
Life of this patent
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Abstract
A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.
Claims19
A receiver with clock phase calibration, the receiver comprising:
- a first sampling circuit to generate first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal;
- a second sampling circuit to generate second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal;
- and
- circuitry to, during a first calibration stage, generate output data of the receiver based on the first digital data and adjust a phase of the second clock signal while the output data is generated from the first digital data, and during a second calibration stage, generate the output data of the receiver based on the second digital data and adjust a phase of the first clock signal while the output data is generated from the second digital data.
A method of operation in a receiver, the method comprising:
- generating first digital data based on an input signal with a first sampling circuit, a sampling phase of the first sampling circuit controlled by a first clock signal;
- generating second digital data based on the input signal with a second sampling circuit, a sampling phase of the second sampling circuit controlled by a second clock signal;
- during a first calibration stage, generating output data of the receiver based on the first digital data and adjusting a phase of the second clock signal while the output data is generated from the first digital data;
- and
- during a second calibration stage, generating the output data of the receiver based on the second digital data and adjusting a phase of the first clock signal while the output data is generated from the second digital data.
Dependencies are inferred from the claim text.