Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes
AssigneeQUALCOMM Incorporated
InventorShoichiro Sengoku
Life of this patent
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Abstract
System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.
Claims26
A method of data communications, comprising:
- monitoring a plurality of data signals carried on a plurality of data lanes of a data communications link and a timing signal carried on a timing lane of the data communications link, wherein the timing signal is a strobe signal that provides timing information corresponding to the plurality of data signals carried on the plurality of data lanes;
- detecting a first-occurring transition on the data communications link, whether the first-occurring transition occurs in a data signal carried on a data lane or in the timing signal carried on the timing lane, and wherein the first-occurring transition occurs at a boundary between a first data period and a second data period;
- generating an edge on a receiver clock signal based on the first-occurring transition, wherein the strobe signal transitions between signaling states when no transition occurs in signaling state of the plurality of data lanes between the first data period and the second data period;
- and
- capturing data received from the plurality of data lanes using the receiver clock signal.
An apparatus comprising:
- means for detecting a first-occurring transition on a data communications link, whether the first-occurring transition occurs in a data lane of a data communications link or in a timing lane of the data communications link, wherein the first-occurring transition occurs at a boundary between a first data period and a second data period, wherein the means for detecting is configured to monitor a plurality of data signals carried on a plurality of data lanes and a timing signal carried on the timing lane, and wherein the timing signal is a strobe signal that provides timing information corresponding to the plurality of data signals carried on the plurality of data lanes;
- means for generating an edge of a receiver clock signal based on the first-occurring transition, wherein the strobe signal transitions between signaling states when no transition occurs in signaling state of the plurality of data lanes between the first data period and the second data period;
- and
- means for decoding data received from the plurality of data lanes using the receiver clock signal.
An apparatus, comprising:
- a processing circuit configured to:
- monitor a plurality of data signals carried on a plurality of data lanes of a data communications link and a timing signal carried on a timing lane of the data communications link, wherein the timing signal is a strobe signal that provides timing information corresponding to the plurality of data signals carried on the plurality of data lanes;
- detect a first-occurring transition on the data communications link, whether the first-occurring transition occurs in a data signal carried on a data lane or in the timing signal carried on the timing lane, wherein the first-occurring transition occurs at a boundary between a first data period and a second data period;
- generate an edge on a receiver clock signal based on the first-occurring transition;
- and
- capture data received from the plurality of data lanes using the receiver clock signal, wherein the strobe signal transitions between signaling states when no transition occurs in signaling state of the plurality of data lanes between the first data period and the second data period.
A non-transitory processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:
- monitor a plurality of data signals carried on a plurality of data lanes of a data communications link and a timing signal carried on a timing lane of the data communications link, wherein the timing signal is a strobe signal that provides timing information corresponding to the plurality of data signals carried on the plurality of data lanes;
- detect a first-occurring transition on the data communications link, whether the first-occurring transition occurs in a data signal carried on a data lane or in the timing signal carried on the timing lane, and wherein the first-occurring transition occurs at a boundary between a first data period and a second data period;
- generate an edge on a receiver clock signal based on the first-occurring transition, wherein the strobe signal transitions between signaling states when no transition occurs in signaling state of the plurality of data lanes between the first data period and the second data period;
- and
- capture data received from the plurality of data lanes using the receiver clock signal.
Dependencies are inferred from the claim text.