Flexible PRBS architecture for a transceiver
AssigneeTexas Instruments Incorporated
InventorsSeuk B. Kim, Tpinn R. Koh
Life of this patent
Estimating the term…
Abstract
An apparatus is provided. The apparatus comprises a polynomial register having a plurality of bits, a first bus, a second bus, and a transceiver that is coupled to the first bus, the second bus, and the polynomial register. The polynomial register is configured to store a user-defined polynomial, and the transceiver includes a pseudorandom bit sequence (PRBS) generator is configured to generate a scrambled signal from the user-defined polynomial and a PRBS checker that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.
Claims20
A transmitter for use in a physical coding sublayer (PCS) of a network transceiver, the transmitter comprising:
- a polynomial register configured to store a user-defined polynomial;
- and
- a pseudorandom bit sequence (PRBS) generator including:
- a matrix circuit coupled with the polynomial register to receive the user-defined polynomial, the matrix circuit configured to generate a P-matrix based on the user-defined polynomial;
- a data register configured to receive a seed vector;
- and
- a multiplier coupled with the matrix circuit and the data register, the multiplier configured to generate a PRBS signal based on the P-matrix and based on data stored in the data register.
A receiver for use in a physical coding sublayer (PCS) of a network transceiver, the receiver comprising:
- a polynomial register configured to store a user-defined polynomial;
- a pseudorandom bit sequence (PRBS) checker including:
- a data bus configured to deliver reception data received by the network transceiver;
- a first matrix circuit coupled with the polynomial register to receive the user-defined polynomial, the first matrix circuit configured to generate a D-matrix based on the user-defined polynomial;
- a first multiplier coupled with the first matrix circuit and the data bus, the first multiplier configured to generate a D-vector by multiplying the D-matrix with the reception data;
- an error detector circuit coupled with the first multiplier to receive the D-vector, the error detector circuit configured to generate an error signal based on the D-vector.
A network transceiver comprising:
- a polynomial register configured to store a user-defined polynomial;
- a pseudorandom bit sequence (PRBS) generator including:
- a first matrix circuit coupled with the polynomial register to receive the user-defined polynomial, the first matrix circuit configured to generate a P-matrix based on the user-defined polynomial;
- and
- a first multiplier coupled with the matrix circuit, the first multiplier configured to generate a PRBS signal based on the P-matrix and based on a seed vector;
- and
- a PRBS checker including:
- a second matrix circuit coupled with the polynomial register to receive the user-defined polynomial, the second matrix circuit configured to generate a D-matrix based on the user-defined polynomial;
- and
- a second multiplier coupled with the second matrix circuit, the second multiplier configured to generate a D-vector by multiplying the D-matrix with input data received by the network transceiver;
- and
- a error detector circuit coupled with the second multiplier to receive the D-vector, the error detector circuit configured to generate an error signal based on the D-vector.
Dependencies are inferred from the claim text.