Variation calibration for envelope tracking on chip
AssigneeMediatek Inc.
InventorsYen-Liang Chen, Chia-Sheng Peng, Da-Wei Sung
Life of this patent
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Abstract
Techniques and examples pertaining to variation calibration for envelope tracking on chip are described. Envelope tracking (ET) statistics among multiple wireless-capable mobile devices (e.g., smartphones) may be collected in laboratory. Optimal ET parameters may be determined based on ET statistics. An ET setting file may be generated for ET factory calibration. In production lines, the ET setting file may be loaded into each mobile device for ET factory calibration.
Claims20
A method of calibrating a plurality of parameters of a semiconductor chip implementable in a wireless communication device, the method comprising:
- performing a first calibration to calibrate a first set of parameters of the plurality of parameters;
- loading a universal setting file comprising a plurality of setting values for a second set of parameters of the plurality of parameters;
- and
- performing a second calibration to calibrate the second set of parameters,
- wherein the plurality of setting values are predetermined by performing a comprehensive calibration matrix across a plurality of sample chips, and
- wherein the plurality of setting values serve as initial calibration values for the second set of parameters.
A method, comprising:
- performing a comprehensive calibration matrix across a plurality of sample chips to determine a plurality of setting values, the performing comprising:
- collecting envelope tracking (ET) statistics among the plurality of sample chips;
- determining a plurality of ET parameters based on the ET statistics;
- and
- generating a universal setting file for the plurality of sample chips based on the plurality of ET parameters.
A variation calibration apparatus that calibrates a plurality of envelope tracking (ET) parameters for a plurality of semiconductor chips having a same circuit design, the circuit design comprising a transmitter (TX), the apparatus comprising:
- a receptacle capable of receiving and operating each of the plurality of semiconductor chips one at a time;
- a variable power supply capable of setting a supply voltage through the receptacle for a respective semiconductor chip of the plurality of semiconductor chips received in the receptacle;
- a test instrument capable of measuring electrical characteristics of the respective semiconductor chip;
- a memory storing a plurality of ET setting combinations based on the plurality of ET parameters, with each of the ET parameters having respective one or more ET parameter settings, and the memory also storing a respective result of an ET measurement for each of the plurality of semiconductor chips;
- and
- a processor communicatively coupled to the receptacle, the variable power supply, the test instrument, and the memory, the processor capable of performing operations comprising:
- performing the ET measurement for each of the plurality of semiconductor chips under one or more of a plurality of measurement conditions and under each of the plurality of ET setting combinations;
- and
- analyzing the respective result of the ET measurement to determine a respective universal ET setting combination for each of one or more measurement conditions, and generating an ET setting file comprising one or more respective universal ET setting combinations for the one or more measurement conditions.
Dependencies are inferred from the claim text.