Parallel-serial conversion circuit, information processing apparatus and timing adjustment method

An information processing apparatus including a parallel-serial conversion circuit, wherein

• the parallel-serial conversion circuit comprises:
• a data transmission unit configured to output first data of a prescribed pattern and second data of the prescribed pattern in accordance with a second clock obtained by dividing a first clock;
• a first flip flop configured to receive the first data so as to output the first data in accordance with the first clock;
• a second flip flop configured to receive the second data so as to output the second data in accordance with the first clock;
• a selector configured to select one of the first data output from the first flip flop and the second data output from the second flip flop so as to output the selected data in accordance with the first clock;
• an XOR circuit configured to output an exclusive OR of the second data to be received by the second flip flop and the first data output from the first flip flop;
• and
• a control circuit configured to adjust, based on the exclusive OR, a timing for the first flip flop to receive the first data.

A timing adjustment method of a parallel-serial conversion circuit, the timing adjustment method comprising:

• outputting, by a data transmission unit, first data of a prescribed pattern and second data of the prescribed pattern in accordance with a second clock obtained by dividing a first clock;
• receiving, by a first flip flop, the first data so as to output the first data in accordance with the first clock,
• receiving, by a second flip flop, the second data so as to output the second data in accordance with the first clock;
• selecting, by a selector, one of the first data output from the first flip flop and the second data output from the second flip flop so as to output the selected data in accordance with the first clock;
• outputting, by an XOR circuit, an exclusive OR of the second data to be received by the second flip flop and the first data output from the first flip flop;
• and
• adjusting, by a control circuit, based on the exclusive OR, a timing for the first flip flop to receive the first data.