US 9,755,659 B2Granted

ASAR ADC circuit and conversion method thereof

AssigneesSemiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation

InventorsBen Peng Xun, Fei Liu, Meng Meng Guo, Hua Tang, Haifeng Yang

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Abstract

The present disclosure provides asynchronous successive approximation register analog-to-digital converter (ASAR ADC) circuits and signal conversion method thereof. An exemplary ASAR AC circuit includes a sample/hold circuit configured to input a first analog signal and output a second analog signal; a digital-to-analog converter circuit configured to output a third analog signal; a first voltage comparison circuit configured to respond to a valid level of a latch signal, and output a first logic level and a second logic level; a first logic circuit configured to respond to a valid level of a flag signal, and identify a comparison result of the first voltage comparison circuit and output the first digit signal; and a pulse generation circuit configured to generate the latch signal and the flag signal with a generation time of the valid levels independently from the first logic level and the second logic level.

Claims20

Dependent claims

An asynchronous successive approximation register analog-to-digital converter (ASAR ADC) circuit, configured to covert a first analog signal into a first digital signal, the ASAR ADC circuit comprising:

a sample/hold circuit having an input terminal configured as an input terminal of the ASAR ADC to input the first analog signal, and an output terminal configured to output a second analog signal;
a digital-to-analog converter circuit having an input terminal configured to input the first digital signal, and an output terminal configured to output a third analog signal;
a first voltage comparison circuit, configured to respond to a valid level of a latch signal, and to compare the second analog signal with the third analog signal respectively inputted into a positive terminal of the first voltage comparison circuit and a negative terminal of the first voltage comparison circuit to output a first logic level and a second logic level;
a first logic circuit, configured to respond to a valid level of a flag signal, and to identify a comparison result of the first voltage comparison circuit according to the first logic level and the second logic level respectively inputted into the first logic circuit to output the first digit signal;
and
a pulse generation circuit configured to generate the latch signal and the flag signal with a generation time of the valid levels of the latch signal and the flag signal independently from the first logic level and the second logic level.

3 more elements

A method for converting a analog signal to a digital signal using an asynchronous successive approximation register analog-to-digital converter (ASAR ADC) circuit having a sample/hold circuit, a digital-to-analog convertor circuit, a first voltage comparison circuit, a first logic circuit and a pulse generation circuit, the method comprising:

inputting a first analog signal into the sample/hold circuit and outputting a second analog signal;
inputting a first digital signal into the digital-to-analog converter circuit and outputting a third analog signal;
responding to a valid level of a latch signal, and comparing the second analog signal with the third analog signal using the first voltage comparison circuit for outputting a first logic level and a second logic level;
responding to a valid level of a flag signal, and identifying a comparison result of the first voltage comparison circuit according to the first logic level and the second logic level using the first logic circuit and outputting a first digital signal;
and
generating the latch signal and the flag signal using the pulse generation circuit with a generation time of the valid levels of the latch signal and the flag signal being independent of the first logic level and the second logic level.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/407,334Filed 17 Jan 2017
Priority: CN 2016 1 00796303 Feb 2016
Published: US 2017/0222654 A13 Aug 2017
Granted: 5 Sep 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H03M 1/125
Details of sampling arrangements or methods: asynchronous, i.e. free-running operation within each conversion cycle
H03M 1/38
Analogue value compared with reference values: sequentially only, e.g. successive approximation type
H03M 1/42
Sequentially only, e.g. successive approximation type: sequential comparisons in series-connected stages with no change in value of analogue signal
H03M 1/44
Sequentially only, e.g. successive approximation type: sequential comparisons in series-connected stages with change in value of analogue signal