Successive approximation register analog-to-digital converter and semiconductor device including the same

A semiconductor device comprising:

• a signal generator configured to generate an input voltage;
• a successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert the input voltage into a digital output signal based on a sampling clock signal;
• and
• a digital signal processing circuit configured to process the digital output signal,
• wherein the SAR ADC comprises:
• a ring oscillator configured to determine a frequency based on a sampling clock signal and a first control code, and generate an output clock signal having the determined frequency;
• and
• a controller configured to generate the first control code based on the frequency of the output clock signal,
• wherein the ring oscillator comprises:
• an output clock signal generation circuit configured to generate the output clock signal based on the sampling clock signal and a feedback clock signal;
• a feedback circuit configured to generate the feedback clock signal;
• and
• a delay adjustment circuit configured to adjust a delay of the output clock signal based on the first control code, and output the delay-adjusted output clock signal to the feedback circuit.

A successive approximation register (SAR) analog-to-digital converter (ADC) comprising:

• a ring oscillator configured to generate an output clock signal based on a sampling clock signal;
• a counter configured to counts a number of times of toggling the output clock signal in a period to generate a count value;
• and
• a controller configured to generate a control code for controlling a frequency of the output clock signal based on the count value,
• wherein the ring oscillator is further configured to generate the output clock signal having the controlled frequency based on the control code, and
• wherein the controller is further configured to:
• determine whether the count value is equal to a reference count value;
• generate a second control code for controlling the frequency to be maintained, in response to a code generator determining that the count value is equal to the reference count value;
• generate the second control code for controlling the frequency to be decreased, in response to the code generator determining that the count value is greater than the reference count value;
• and
• generate the second control code for controlling the frequency to be increased, in response to the code generator determining that the count value is less than the reference count value.