Multiplexer-memory cell circuit, layout thereof and method of manufacturing same
AssigneeFlex Logix Technologies, Inc.
InventorCheng C. Wang
Life of this patent
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Abstract
An integrated circuit includes a field programmable gate array including: (i) a plurality of memory cells (e.g., static memory cells) to store data, wherein each memory cell includes a first output, (ii) a multiplexer including inputs, an output and input selects, (iii) a plurality of poly-silicon conductors, each poly-silicon conductor is disposed in the substrate and connected to the first output of an associated memory cell, (iv) poly-silicon extensions, each poly-silicon extension is (a) connected to an associated poly-silicon conductor and (b) coupled to an associated input select of the multiplexer, wherein the poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor in the field programmable gate array.
Claims20
An integrated circuit disposed in and on a substrate, the integrated circuit comprising:
- a field programmable gate array including:
- a plurality of memory cells to store data, wherein each memory cell includes a first output;
- a multiplexer including a plurality of inputs, an output and a plurality of input selects;
- a first plurality of poly-silicon conductors, each poly-silicon conductor is disposed in the substrate and connected to the first output of an associated memory cell;
- and
- a first plurality of poly-silicon extensions, each poly-silicon extension is (i) connected to an associated poly-silicon conductor of the first plurality of poly-silicon conductors and (ii) coupled to an associated input select of the multiplexer, wherein the first plurality of poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor in the field programmable gate array.
An integrated circuit disposed in and on a substrate, the integrated circuit comprising:
- a field programmable gate array including:
- a plurality of memory cells to store data, wherein each memory cell includes a first output;
- a first multiplexer including a plurality of inputs, an output and a plurality of input selects;
- a first plurality of poly-silicon conductors, each poly-silicon conductor of the first plurality is disposed in the substrate and connected to the first output of an associated memory cell;
- a first plurality of poly-silicon extensions, each poly-silicon extension having a first end and a second end, wherein each poly-silicon extension of the first plurality is (i) connected at a first end to an associated poly-silicon conductor of the first plurality of poly-silicon conductors and (ii) coupled at a second end to an associated input select of the first multiplexer, wherein the first plurality of poly-silicon extensions are disposed in the substrate and at least partially under a first metal conductor in the field programmable gate array;
- a second multiplexer including a plurality of inputs, an output and a plurality of input selects;
- and
- a second plurality of poly-silicon extensions, each poly-silicon extension of the second plurality having a first end and a second end, wherein each poly-silicon extension of the second plurality is (i) coupled at a first end to a second end of a unique poly-silicon extension of the first plurality of poly-silicon extensions and (ii) coupled at a second end to an associated input select of the second multiplexer, wherein the second plurality of poly-silicon extensions are disposed in the substrate and at least partially under a second metal conductor in the field programmable gate array.
An integrated circuit disposed in and on a substrate, the integrated circuit comprising:
- a field programmable gate array including:
- a plurality of static memory cells to store data, wherein each memory cell includes a first output;
- a multiplexer including a plurality of inputs, an output and a plurality of input selects;
- a first plurality of poly-silicon conductors, each poly-silicon conductor is disposed in the substrate and connected to the first output of an associated memory cell;
- poly-silicon extensions, each poly-silicon extension is (i) connected to an associated poly-silicon conductor of the first plurality of poly-silicon conductors and (ii) coupled to an associated input select of the multiplexer, wherein the poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor in the field programmable gate array;
- and
- a second plurality of poly-silicon conductors, each poly-silicon conductor of the second plurality includes first and second ends and is disposed in the substrate, wherein the first end is connected to the associated poly-silicon extension and the second end is connected at the associated input select of the multiplexer.
Dependencies are inferred from the claim text.