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US 9,755,646 B2Granted
Input/output buffer circuit for avoiding malfunctioning in processing signals
AssigneeNuvoton Technology Corporation
InventorCheng-Chih Wang
Life of this patent
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Abstract
An input/output (I/O) buffer circuit includes an I/O unit, a first register and a second register. The I/O unit selectively transmits digital signals and analog signals according to a first enable signal, and selectively receives signals and outputs signals at an I/O terminal according to a second enable signal. The first register latches a first control signal received before power is turned off, and outputs the first enable signal corresponding to the first control signal to the I/O unit when power is turned on. The second register latches a second control signal received before power is turned off, and outputs the second enable signal corresponding to the second control signal to the I/O unit when power is turned on.
Claims14
An input/output (I/O) buffer circuit comprising:
- an I/O unit configured to selectively transmit digital signals and analog signals according to a first enable signal, and selectively receive signals and output signals at an I/O terminal according to a second enable signal;
- a first register configured to latch a first control signal received before power is turned off, and output the first enable signal corresponding to the first control signal to the I/O unit when power is turned on, wherein the first register is a non-volatile register;
- a second register configured to latch a second control signal received before power is turned off, and output the second enable signal corresponding to the second control signal to the I/O unit when power is turned on, wherein the second register is a non-volatile register;
- a first resistive random access memory element configured to temporarily store the first control signal received by the first register into a first resistive state before power is turned off, and the first resistive random access memory element is disposed inside the first register, wherein the power is turned on, the first register transforms the first resistive state into the first enable signal, and outputs the first enable signal which is corresponding to the first control signal to the I/O unit;
- a second resistive random access memory element configured to temporarily store the second control signal received by the second register into a second resistive state before power is turned off, and the second resistive random access memory element is disposed inside the second register, wherein the power is turned on, the second register transforms the second resistive state into the second enable signal, and outputs the second enable signal which is corresponding to the second control signal to the I/O unit;
- and
- a third register configured to latch a process signal received before power is turned off, and output an output signal corresponding to the process signal to the I/O unit when power is turned on, such that the I/O unit outputs the output signal at the I/O terminal according to the first enable signal and the second enable signal.
4 more elements
An input/output (I/O) buffer circuit comprising:
- a first non-volatile register configured to output a first enable signal when a power-off state resumes to a power-on state;
- a second non-volatile register configured to output a second enable signal when the power-off state resumes to the power-on state;
- an I/O unit, in a state where the first enable signal and the second enable signal separately have a predetermined logic level, configured to be controlled by the first enable signal and the second enable signal to receive and deliver an analog input signal to an input terminal when the power-off state resumes to the power-on state;
- a first resistive random access memory element configured to temporarily store the first control signal received by the first non-volatile register into a first resistive state before power is turned off, and the first resistive random access memory element is disposed inside the first non-volatile register, wherein the power is turned on, the first non-volatile register transforms the first resistive state into the first enable signal, and outputs the first enable signal which is corresponding to the first control signal to the I/O unit;
- a second resistive random access memory element configured to temporarily store the second control signal received by the second non-volatile register into a second resistive state before power is turned off, and the second resistive random access memory element is disposed inside the second non-volatile register, wherein the power is turned on, the second non-volatile register transforms the second resistive state into the second enable signal, and outputs the second enable signal which is corresponding to the second control signal to the I/O unit;
- and
- a third non-volatile register configured to output an output signal to the I/O unit when the power-off state resumes to the power-on state, such that the I/O unit outputs the output signal at an I/O terminal according to the first enable signal and the second enable signal.
4 more elements
Dependencies are inferred from the claim text.