Semiconductor device including buffer circuit and level shifter circuit, and electronic device including the same

A semiconductor device comprising:

• a first wiring configured to supply a first potential;
• a second wiring configured to supply a second potential, the second potential being higher than the first potential;
• a third wiring configured to supply a third potential, the third potential being lower than the first potential and the second potential;
• a first buffer circuit electrically connected to the first wiring and the third wiring;
• and
• a level shifter circuit electrically connected to the second wiring and the third wiring, the level shifter circuit comprising a first node, a second node, a first capacitor, a second capacitor, a first transistor, a second transistor, and a third transistor,
• wherein the first node is configured to hold the second potential when a low-level potential is output from the level shifter circuit,
• wherein the second node is configured to hold the third potential when the low-level potential is output from the level shifter circuit,
• wherein a first electrode of the first capacitor and one of a source and a drain of the first transistor are electrically connected to the second wiring,
• wherein a second electrode of the first capacitor and a gate of the first transistor are electrically connected to the first node,
• wherein a first electrode of the second capacitor and one of a source and a drain of the second transistor are electrically connected to the third wiring,
• wherein a second electrode of the second capacitor and the other of the source and the drain of the second transistor are electrically connected to the second node, and
• wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
• wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,
• wherein the first capacitor and the second capacitor are provided over the first transistor, the second transistor, and the third transistor with an insulating layer and a wiring therebetween.