Apparatus and method for reducing di/dt during power wake-up
AssigneeIntel Corporation
InventorsYong Shim, Jaydeep P. Kulkarni, Pascal A. Meinerzhagen, Muhammad M. Khellah
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Abstract
Described is an apparatus which comprises: a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal; a resistive device; a first transistor coupled in series with the resistive device together forming a pair, the first transistor also coupled to the gate terminal of the power gate transistor; a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.
Claims20
An apparatus comprising:
- a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal;
- a resistive device;
- a first transistor coupled in series with the resistive device and together forming a pair, the first transistor also connected to the gate terminal of the power gate transistor;
- a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device;
- and
- a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.
An apparatus comprising:
- a first modular primary power gate;
- and
- a second modular primary power gate coupled in a sequence with the first modular primary power gate, wherein the second modular primary power gate is to turn on after the first modular primary power gate is to turn on, wherein at least one of the first and second modular primary power gates includes:
- a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal;
- a resistive device;
- a first transistor coupled in series with the resistive device together forming a pair, the first transistor also connected to the gate terminal of the power gate transistor;
- a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device;
- and
- a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.
A system comprising:
- a memory;
- a processor coupled to the memory, the processor including an apparatus which includes:
- a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal;
- a resistive device;
- a first transistor coupled in series with the resistive device together forming a pair, the first transistor also connected to the gate terminal of the power gate transistor;
- a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device;
- and
- a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node;
- and
- a wireless interface for allowing the processor to communicate with another device.
Dependencies are inferred from the claim text.