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US 9,755,626 B2Granted
Semiconductor integrated circuit device having delay circuit
AssigneeSK hynix Inc.
InventorsSung Yub Lee, Jae Hoon Cha
Life of this patent
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Abstract
A semiconductor integrated circuit device may include a first circuit, a second circuit, and a delay circuit. The first circuit may include an output node. The second circuit may include an output node. The delay circuit may be coupled between the output node of the first circuit and the output node of the second circuit to selectively delay an output signal from the first circuit and an output signal from the second circuit.
Claims11
A semiconductor integrated circuit device comprising:
- a first circuit having an output node;
- a second circuit having an output node;
- and
- a delay circuit coupled between the output node of the first circuit and the output node of the second circuit to selectively delay one of an output signal of the first circuit and an output signal of the second circuit,
- wherein the first circuit comprises a word line controlling circuit configured to generate a signal for activating a word line of a memory device, and
- wherein the second circuit comprises an equalizing control circuit configured to generate a signal for equalizing a bit line of the memory device to a predetermined voltage.
3 more elements
A semiconductor integrated circuit device comprising:
- a word line controlling circuit configured to generate a word line control signal for activating an word line in response to an active signal;
- an equalizing control circuit configured to generate a bit line equalizing signal in response to the active signal;
- and
- a delay circuit coupled between an output node of the word line controlling circuit and an output node of the equalizing control circuit, in common, and to selectively delay one of the word line control signal and the equalizing signal,
- wherein the delay circuit comprises:
- a selecting circuit configured to select one of the word line control signal and the bit line equalizing signal in accordance with a first node selection signal and a second node selection signal;
- an enabling circuit coupled to the selecting circuit to determine operations of the delay circuit, the enabling circuit including an NMOS transistor driven in response to an enabling signal;
- and
- a delaying unit coupled to the enabling circuit,
- wherein the enabling signal is activated when a voltage level of the first node selection signal is different from that of the second node selection signal, and the enabling signal is deactivated when the voltage level of the first node selection signal is the same as that of the second node selection signal.
7 more elements
Dependencies are inferred from the claim text.