Device for detecting and correcting timing error and method for designing typical-case timing using the same

A device for detecting and correcting timing error comprising:

• two datapath units each having an input terminal and an output terminal, and each said datapath unit uses said input terminal thereof to receive an input signal, calculates said input signal and uses said output terminal thereof to generate and output a speculation value and a correct value;
• a first multiplexer connected with said output terminal of each said datapath unit to receive and output said speculation value outputted by each said datapath unit;
• a second multiplexer connected with said output terminal of each said datapath unit to receive and output said correct value outputted by each said datapath unit;
• two transition detectors respectively connected with said output terminals of said datapath units, and when one of said datapath units outputs said speculation value, its corresponding said transition detector determines whether transition at said output terminal of said datapath unit corresponded thereof is stable, and when said transition is unstable, said transition detector outputs a wait signal, and when said transition is stable, said transition detector directly outputs said speculation value;
• and
• a control logic gate connected with said transition detectors to receive said wait signal outputted by one of said transition detectors, outputting it, and stalling said datapath unit outputting said speculation value for a period of time, whereby said second multiplexer outputs said correct value and said first multiplexer corrects said speculation value and then outputs it.