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US 9,755,619 B2Granted
Rail-to-rail comparator with shared active load
AssigneeNXP USA, Inc.
InventorsHao Zhi, Jie Jin, Yang Wang, Jianzhou Wu
Life of this patent
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Abstract
A rail-to-rail comparator circuit includes NMOS and PMOS differential input stages with associated loads that are coupled to a shared-load stage. The shared-load stage is coupled to an output stage that includes two active devices. By sharing the load stage between the two input stages, the comparator has a relatively small circuit area, low power draw, and low propagation delay with rail-to-rail input common-mode voltage range.
Claims15
A comparator, comprising:
- a n-type input stage connected to receive a differential input signal comprising a negative input component and a positive input component, wherein the n-type input stage comprises a differential pair of input n-channel transistors having their sources connected to a current sink, and a pair of active load p-channel transistors having their sources connected together, and their gates connected together and to a drain of a first one of the input n-channel transistors;
- a p-type input stage connected to receive the differential input signal, wherein the p-type input stage comprises a differential pair of input p-channel transistors having their sources connected to a current source, and a pair of active load n-channel transistors having their sources connected together, and their gates connected together and to a drain of a first one of the input p-channel transistors;
- a shared-load stage connected to both the n-type input stage and the p-type input stage and comprising load devices that are shared by both the n-type input stage and the p-type input stage;
- and
- an output stage connected to the shared-load stage, wherein the output stage comprises a first output transistor having a source connected to the sources of the active load p-channel transistors and a gate connected to the shared-load stage, and a second output transistor having a source connected to the sources of the active load n-channel transistors and a gate connected to the shared-load stage, and configured to present a comparator output signal indicative of relative voltage levels of the differential input signal at a node between the drains of the first and second output transistors,
- wherein the p-type input stage is configured to be inactive, if a common-mode voltage of the differential input signal is substantially close to a power rail of the comparator, and the n-type input stage is configured to be inactive, if the common-mode voltage of the differential input signal is substantially close to a ground rail of the comparator.
3 more elements
A comparator, comprising:
- an NMOS-input stage comprising a differential pair of source-coupled n-type transistors and one or more NMOS-input stage active-load transistors, wherein a first of the source-coupled n-type transistors is electrically connected via its gate node to a positive differential input node and a second of the n-type transistors is electrically connected at its gate node to a negative input node, wherein the NMOS-input stage active-load transistors have their gates connected together and to a drain of one of the differential pair of source-coupled n-type transistors, and the sources of the differential pair of source-coupled n-type transistors are connected to a current sink;
- a PMOS-input stage comprising a differential pair of source-coupled p-type transistors and one or more PMOS-input stage active-load transistors, wherein a first of the source-coupled p-type transistors is electrically connected via its gate node to the positive differential input node and a second of the source-coupled p-type transistors is electrically connected via its gate node to the negative input node, wherein the PMOS-input stage active-load transistors have their gates connected together and to a drain of one of the differential pair of source-coupled p-type transistors, and the sources of the differential pair of source-coupled p-type transistors are connected to a current source;
- a shared-load stage comprised of first and second active-load transistors that are electrically connected between the PMOS-input stage and the NMOS-input stage, wherein the first active-load transistor of the shared-load stage has a source connected to the sources of the NMOS-input stage active-load transistors, a drain connected to the drain of one of the differential pair of source-coupled n-type transistors of the NMOS input stage, and a gate connected to its drain, and the second active-load transistor of the shared-load stage is connected between the active-load transistors of the NMOS- and PMOS-input stages;
- and
- an output stage that includes no more than two transistors, wherein gates of the output stage transistors are electrically connected to gates of the first and second active-load transistors of the shared-load stage,
- wherein in operation, when the NMOS-input stage is active, the current is drawn through at least one of the active-load transistors within the shared-load stage, and when the PMOS-input stage is active, the current is drawn through the same at least one of the active-load transistors within the shared-load stage.
3 more elements
Dependencies are inferred from the claim text.