US 9,755,618 B1Granted

Low-area low clock-power flip-flop

AssigneeQUALCOMM Incorporated

InventorsSeid Hadi Rasouli, Xiangdong Chen, Venugopal Boynapalli

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Abstract

In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.

Claims19

Dependent claims

A flip-flop comprising:

a first AND gate including a first AND gate first input, a first AND gate second input, and a first AND gate output, the first AND gate first input being a delay (d) input of the flip-flop;
a first NOR gate including a first NOR gate first input, a first NOR gate second input, and a first NOR gate output, the first AND gate output coupled to the first NOR gate first input;
a second NOR gate including a second NOR gate first input, a second NOR gate second input, and a second NOR gate output, the first NOR gate output coupled to the second NOR gate first input, the second NOR gate output coupled to the first NOR gate second input;
a first inverter including a first inverter input and a first inverter output, the first inverter input configured to receive a clock signal, the first inverter output configured to output an inverted clock signal, the first inverter output coupled to the first AND gate second input and the second NOR gate second input;
a second AND gate including a second AND gate first input, a second AND gate second input, and a second AND gate output, the second AND gate first input coupled to the first inverter output;
a third NOR gate including a third NOR gate first input, a third NOR gate second input, and a third NOR gate output, the third NOR gate first input coupled to the second NOR gate output, the third NOR gate second input coupled to the second AND gate output;
and
a second inverter including a second inverter input and a second inverter output, the second inverter output coupled to the second AND gate second input.

5 more elements

A method of an AND-OR-Inverter (AOI) based flip-flop operation comprising:

inputting a clock signal to the AOI based flip-flop;
and
inputting an input value to the AOI based flip-flop on a delay (d) input;
the AOI based flip-flop including:
a first AND gate including a first AND gate first input, a first AND gate second input, and a first AND gate output, the first AND gate first input being the d input of the AOI based flip-flop;
a first NOR gate including a first NOR gate first input, a first NOR gate second input, and a first NOR gate output, the first AND gate output coupled to the first NOR gate first input;
a second NOR gate including a second NOR gate first input, a second NOR gate second input, and a second NOR gate output, the first NOR gate output coupled to the second NOR gate first input, the second NOR gate output coupled to the first NOR gate second input;
a first inverter including a first inverter input and a first inverter output, the clock signal coupled to the first inverter input, an inverted clock signal output from the first inverter output, the first inverter output coupled to the first AND gate second input and the second NOR gate second input;
a second AND gate including a second AND gate first input, a second AND gate second input, and a second AND gate output, the second AND gate first input coupled to the first inverter output;
a third NOR gate including a third NOR gate first input, a third NOR gate second input, and a third NOR gate output, the third NOR gate first input coupled to the second NOR gate output, the third NOR gate second input coupled to the second AND gate output;
and
a second inverter including a second inverter input and a second inverter output, the second inverter output coupled to the second AND gate second input.

9 more elements

An AOI based flip-flop comprising:

means for inputting a clock signal to the AOI based flip-flop;
and
means for inputting an input value to the AOI based flip-flop on a delay (d) input;
the AOI based flip-flop including:
a first AND gate including a first AND gate first input, a first AND gate second input, and a first AND gate output, the first AND gate first input being the d input of the AOI based flip-flop;
a first NOR gate including a first NOR gate first input, a first NOR gate second input, and a first NOR gate output, the first AND gate output coupled to the first NOR gate first input;
a second NOR gate including a second NOR gate first input, a second NOR gate second input, and a second NOR gate output, the first NOR gate output coupled to the second NOR gate first input, the second NOR gate output coupled to the first NOR gate second input;
a first inverter including a first inverter input and a first inverter output, the clock signal coupled to the first inverter input, an inverted clock signal output from the first inverter output, the first inverter output coupled to the first AND gate second input and the second NOR gate second input;
a second AND gate including a second AND gate first input, a second AND gate second input, and a second AND gate output, the second AND gate first input coupled to the first inverter output;
a third NOR gate including a third NOR gate first input, a third NOR gate second input, and a third NOR gate output, the third NOR gate first input coupled to the second NOR gate output, the third NOR gate second input coupled to the second AND gate output;
and
a second inverter including a second inverter input and a second inverter output, the second inverter output coupled to the second AND gate second input.

9 more elements

Dependencies are inferred from the claim text.