Settling time reduction for low noise amplifier

An amplifier, comprising:

• an amplifying transistor having an input terminal configured to receive an input signal and to amplify the input signal;
• an adjustable current source configured to set a bias current of the input terminal of the amplifying transistor, the adjustable current source having a control input for receiving a digital control word for selecting the bias current to have one of a plurality of selectable bias current levels;
• a first resistor and a second resistor connected in series between the adjustable current source and the input terminal of the amplifying transistor;
• a transistor switch connected across the second resistor for selectively bypassing the second resistor;
• and
• a control circuit connected to a control terminal of the transistor switch, wherein the control circuit comprises:
• a plurality of bit transition detection circuits each corresponding to one of the plurality of bits of the digital control word, each bit transition detection circuit comprising:
• at least two inverters and a delay circuit arranged in series and configured to receive the corresponding one of the plurality of bits, and to output a corresponding delayed bit, and
• an exclusive OR (XOR) gate configured to receive the corresponding one of the plurality of bits, and the corresponding delayed bit and in response thereto to output a bit change detection pulse when a value of the corresponding one of the plurality of bits changes, and
• a logic circuit configured to logically combine output signals of the XOR gates of the bit transition detection circuits and to produce a control pulse for controlling the transistor switch to bypass the second resistor for a predefined time period in response to a bit change detection pulse in any of the outputs of the bit transition detection circuits.