Semiconductor device for controlling power-up sequences
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-cheol Kim, Seung-jun Bae
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Abstract
A semiconductor device for controlling a power-up sequence is provided. The semiconductor device includes a plurality of chips. Each of the chips includes a power-up sequence controller configured to differently control generation sequences of internal source voltages. The power-up sequence controller changes the generation sequences of the internal source voltages in response to a power stabilization signal which is generated according to an external source voltage applied thereto in powering up the semiconductor device. Accordingly, a power-up current which is generated according to the internal source voltages being generated has a peak current distribution where a peak current may be equally distributed.
Claims20
A semiconductor device comprising:
- a first chip comprising:
- a first voltage generator configured to generate a first plurality of internal source voltages including a first internal source voltage having a first voltage value, a second internal source voltage having a second voltage value, and a third internal source voltage having a third voltage value, wherein the first, second, and third voltage values are different from each other, and
- a first power-up sequence controller configured to control a first sequence of generating by the first voltage generator the first internal source voltage, the second internal source voltage, and the third internal source voltage;
- and
- a second chip comprising:
- a second voltage generator configured to generate a second plurality of internal source voltages including a fourth internal source voltage having the first voltage value, a fifth internal source voltage having the second voltage value, and a sixth internal source voltage having the third voltage value, and
- a second power-up sequence controller configured to control a second sequence of generating by the second voltage generator the fourth internal source voltage, the fifth internal source voltage, and the sixth internal source voltage,
- wherein the first sequence is different from the second sequence.
A multi-chip package comprising:
- a first memory chip comprising:
- a first voltage generator configured to generate a first plurality of internal source voltages having first values, the first values including a first internal source voltage value, a second internal source voltage value, and a third internal source voltage value;
- and
- a first power-up sequence controller configured to control a generation sequence of the first plurality of internal source voltages generated by the first voltage generator;
- a second memory chip comprising:
- a second voltage generator configured to generate a second plurality of internal source voltages having second values, the second values including the first internal source voltage value, the second internal source voltage value, and the third internal source voltage value;
- and
- a second power-up sequence controller configured to control a generation sequence of the second plurality of internal source voltages generated by the second voltage generator,
- wherein the first, second, and third internal source voltage values are different from each other, and
- wherein the first power-up sequence controller sets the generation sequence of the first plurality of internal source voltages different from the generation sequence of the second plurality of internal source voltages thereby distributing a peak current of a power-up current in powering up the multi-chip package.
A method for controlling a power-up sequence of a multi-chip package including a first memory chip and a second memory chip, the method comprising:
- generating, by a first power-up sequence controller of the first memory chip, a first operational sequence of operation of a first plurality of voltage generation circuits;
- transmitting the first operational sequence from the first power-up sequence controller to the first plurality of voltage generation circuits;
- generating, by a second power-up sequence controller of the second memory chip, a second operational sequence of operation of a second plurality of voltage generation circuits, the second operational sequence being different from the first operational sequence;
- transmitting the second operational sequence from the second power-up sequence controller to the second plurality of voltage generation circuits;
- and
- generating at power-up of the multi-chip package, by each of the first and second pluralities of voltage generation circuits, power-up voltages according to the first and second operational sequences.
Dependencies are inferred from the claim text.