Current clamp circuit based on BCD technology

A current clamp circuit based on Bipolar-CMOS-DMOS technology, being characterized in comprising a current-outputting circuit, an output-current-sensing circuit, and a current clamp circuit, the current-outputting circuit having an input end connected to a high-voltage input voltage (VIN), the current-outputting circuit having an output end connected to an input end of the output-current-sensing circuit, the output-current-sensing circuit having an output end connected to an input end of the current clamp circuit, and the current clamp circuit having an output end connected to a feedback control end of the current-outputting circuit,

• wherein the current-outputting circuit comprising low-voltage PMOS tubes (M1, M2), an amplifier (OP1), high-voltage LDPMOS tubes (M3, M4), and a reference current source (I-ref1), the low-voltage PMOS tube (M1) having an M value of 1, the low-voltage PMOS tube (M2) having an M value that is a predetermined value designated at K, the low-voltage PMOS tubes (M1, M2) forming a first current mirror, the high-voltage LDPMOS tubes (M3, M4) having gates thereof commonly connected to a bias voltage (V_bias_1), the reference current source (I-ref1) being connected in series with and between a drain of the high-voltage LDPMOS tube (M3) and the ground, the high-voltage LDPMOS tube (M4) having a drain that acts as an output port;
• the high-voltage LDPMOS tubes (M3, M4) having sources thereof connected to two input ends of the amplifier (OP1), respectively and connected to drains of the low-voltage PMOS tubes (M1, M2), respectively, the amplifier (OP1) having an output end connected to gates of the low-voltage PMOS tubes (M1, M2), and the low-voltage PMOS tubes (M1, M2) having sources thereof connected to the high-voltage input voltage (VIN);
• the output-current-sensing circuit comprising low-voltage PMOS tubes (M5, M7), a high-voltage LDPMOS tube (M6), and an amplifier (OP2), the low-voltage PMOS tubes (M5, M7) both having an M value of 1, the low-voltage PMOS tube (M5) and the low-voltage PMOS tube (M2) forming a second current mirror, the low-voltage PMOS tube (M5) having a source connected to the high-voltage input voltage (VIN), the amplifier (OP2) having two input ends connected to drains of the low-voltage PMOS tube (M2, M5), respectively, the amplifier (OP2) having an output end connected to a gate of the high-voltage LDPMOS tube (M6), the high-voltage LDPMOS tube (M6) having a source connected to a drain of the low-voltage PMOS tube (M5), the high-voltage LDPMOS tube (M6) having a drain connected to a drain and a gate low-voltage PMOS tube (M7), and the low-voltage PMOS tube (M7) having a source connected to the ground;
• the current clamp circuit comprising a low-voltage PMOS tube (M8), high-voltage LDPMOS tubes (M9, M10), a reference current source (I-ref2), and an amplifier (OP3), the low-voltage PMOS tube (M8) having an M value of 1, the low-voltage PMOS tube (M7) and the low-voltage PMOS tube (M8) forming a third current mirror, the low-voltage PMOS tube (M8) having a drain connected to a source of the high-voltage LDPMOS tube (M9), the high-voltage LDPMOS tubes (M9, M10) having gates thereof connected to a bias voltage (V_bias_2), the reference current source (I-ref2) being connected in series with and between a source of the high-voltage LDPMOS tube (M10) and the ground, the high-voltage LDPMOS tubes (M9, M10) having drains thereof connected to input ends of the amplifier (OP3), respectively, and connected to the high-voltage input voltage (VIN) through resistors (R1, R2) that have an identical level of resistance, respectively, and the amplifier (OP3) having an output end connected to a feedback control end of the amplifier (OP1).