Semiconductor device and method of manufacturing the same

A semiconductor device, comprising:

• memory blocks each configured to comprise a pipe gate and channels, each channel including a pipe channel formed in the pipe gate and a pair of a drain-side channel and a source-side channel coupled to the pipe channel;
• insulating layers placed between the memory blocks adjacent to other memory blocks, and interposed between pipe gates of the memory blocks to insulate the pipe gates from each other;
• first slits placed between the memory blocks adjacent to other memory blocks and placed above the insulating layers;
• a second slit placed between the source-side channel and the drain-side channel of each pair of channels;
• third slits placed between the drain-side channels adjacent to other drain-side channels, wherein a drain-side word line and a drain select line of the drain-side channels adjacent to other drain-side channels are separated from each other by the third slits interposed therebetween;
• and
• fourth slits placed between the source-side channels adjacent to other source-side channels and formed to generally the same depth as source select lines, wherein the source select lines of the source-side channels adjacent to other source-side channels are separated from each other by the fourth slits interposed therebetween and the source-side channels adjacent to each other share a source-side word line.

A semiconductor device, comprising:

• memory blocks each configured to comprise a pipe gate and channels, each channel including a pipe channel formed in the pipe gate and a pair of a drain-side channel and a source-side channel coupled to the pipe channel;
• insulating layers placed between the memory blocks adjacent to other memory blocks, and interposed between the pipe gates of the memory blocks to insulate the pipe gates from each other;
• first slits placed between the memory blocks adjacent to other memory blocks and placed above the insulating layers;
• a second slit placed between the source-side channel and the drain-side channel of each pair of channels;
• third slits placed between the source-side channels adjacent to other source-side channels, wherein a source-side word line and a source select line of the adjacent channels are separated from each other by the third slits interposed therebetween;
• and
• fourth slits placed between the drain-side channels adjacent to other drain-side channels and formed to generally the same depth as drain select lines, wherein the drain select lines of the drain-side channels adjacent to other drain-side channels are separated from each other by the fourth slits interposed therebetween,
• wherein the drain-side channels adjacent to each other share a drain-side word line.

A semiconductor device, comprising:

• memory blocks each configured to comprise a pipe gate and channels, each channel including a pipe channel formed in the pipe gate and a pair of a drain-side channel and a source-side channel coupled to the pipe channel;
• insulating layers placed between the memory blocks adjacent to other memory blocks, and interposed between the pipe gates of the memory blocks to insulate the pipe gates from each other;
• first slits placed between the memory blocks adjacent to other memory blocks and placed above the insulating layers;
• a second slit placed between the source-side channel and the drain-side channel of each pair of channels;
• and
• at least one fifth slit placed substantially within a slimming region of the memory block, generally in a circumference of the slimming region, or substantially within the slimming region and generally in the circumference of the slimming region, wherein the memory block includes a cell region where the channels are located and the slimming region located at both sides of the cell region.

A semiconductor device, comprising:

• a substrate including a source line therein;
• memory blocks each configured to include channels coupled to the source line and protruded from the substrate, wherein each of the memory blocks includes a cell region where the channels are located and a slimming region located at both sides of the cell region, and the cell region and the slimming region are arranged in a direction parallel to a surface of the substrate;
• at least one first slit placed in the slimming region of the memory block;
• at least one second slit formed in the cell region of the memory block and placed between the channels;
• and
• third slits placed between the memory blocks adjacent to each other.