Source and drain stressors with recessed top surfaces
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
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Abstract
An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.
Claims20
A method comprising:
- forming a first gate stack over a semiconductor substrate;
- forming a first opening extending into the semiconductor substrate, wherein the first opening is adjacent to the first gate stack;
- and
- performing an epitaxy to grow a first semiconductor region in the first opening, wherein the first semiconductor region comprises a different material than the semiconductor substrate, wherein the first semiconductor region comprises a first top surface extending above an interface between the first gate stack and the semiconductor substrate, wherein performing the epitaxy comprises controlling epitaxy parameters so that a center portion of the first top surface is recessed lower than first and second portions of the first top surface to form a recess, and wherein the first and second portions are on opposite sides of the center portion.
A method comprising:
- forming a first gate stack over a semiconductor substrate;
- patterning a first opening extending into the semiconductor substrate and adjacent to the first gate stack;
- epitaxially growing a first semiconductor region in the first opening and comprising a different material than the semiconductor substrate, wherein the first semiconductor region comprises a first top surface extending above an interface between the first gate stack and the semiconductor substrate, and wherein the first top surface comprises a first center portion recessed from a first portion of the first top surface;
- forming a second gate stack over the semiconductor substrate;
- patterning a second opening extending into the semiconductor substrate and adjacent to the second gate stack;
- and
- epitaxially growing a second semiconductor region in the second opening and comprising a different material than the semiconductor substrate, wherein the second semiconductor region comprises a second top surface extending above an interface between the second gate stack and the semiconductor substrate, and wherein the second top surface has a different profile than the first top surface.
The method of claim ii, wherein the one or more process gases comprise HCl, GeH4, Dichloro-Silane (DCS), or a combination thereof.
A method comprising:
- patterning a first opening and a second opening extending into a semiconductor substrate;
- epitaxially growing a first silicon germanium region in the first opening, wherein the first silicon germanium region comprises a first top surface, and wherein the first top surface comprises a first center portion recessed from and disposed between a first portion of the first top surface and a second portion of the first top surface;
- and
- while epitaxially growing the first silicon germanium region, epitaxially growing a second silicon germanium region in the second opening, wherein the second silicon germanium region comprises a second top surface, and wherein a center portion of the second top surface is higher than an edge portion of the second top surface.
Dependencies are inferred from the claim text.