Semiconductor device including a multi-channel active pattern

A semiconductor device, comprising:

• a first multi-channel active pattern;
• afield insulation layer disposed on the first multi-channel active pattern and including a first region and a second region, the first region having a top surface protruding from a top surface of the second region to a top surface of the first multi-channel active pattern;
• a first gate electrode crossing the first multi-channel active pattern, the first gate electrode being disposed on the field insulation layer;
• a first source or drain disposed between the first gate electrode and the first region of the field insulation layer and including a first facet that is a slanted sidewall, the first facet being disposed adjacent to the first region of the field insulation layer at a point lower than the top surface of the first multi-channel active pattern;
• a second multi-channel active pattern parallel with the first multi-channel active pattern, the first region of the field insulation layer being interposed between the first multi-channel active pattern and the second multi-channel active pattern;
• a second gate electrode crossing the second multi-channel active pattern, the second gate electrode being disposed on the field insulation layer;
• and
• a second source or drain disposed between the second gate electrode and the first region of the field insulation layer,
• wherein the second source or drain includes a second facet disposed adjacent to the sidewall of the first region of the field insulation layer.

A semiconductor device, comprising:

• a multi-channel active pattern;
• a field insulation layer disposed on at least two sides of the multi-channel active pattern and including a first region and a second region;
• a dummy gate electrode disposed on the first region of the field insulation layer;
• a gate electrode crossing the multi-channel active pattern, the gate electrode being disposed on the second region of the field insulation layer, the gate electrode having a height greater than that of the dummy gate electrode;
• and
• a source or drain disposed between the gate electrode and the dummy gate electrode and including a facet,
• wherein the facet is adjacent to a sidewall of the first region of the field insulation layer.

A semiconductor device, comprising:

• a multi-channel active pattern;
• a field insulation layer disposed on first and second sides of the multi-channel active pattern, the field insulation layer including a first region extending to a top surface of the multi-channel active pattern;
• a gate electrode overlapping the multi-channel active pattern and disposed on the field insulation layer on the first and second sides of the multi-channel active pattern;
• and
• a source or drain disposed between the gate electrode and the first region of the field insulation layer, the source or drain including a slanted edge that extends from the first region of the field insulation layer to a spacer adjacent to the gate electrode.