High voltage device fabricated using low-voltage processes

A method for fabricating a high-voltage transistor on a semiconductor substrate comprising:

• defining and forming shallow trench isolation regions in the semiconductor substrate for all of the transistors to be formed in the integrated circuit;
• defining and forming well regions in the semiconductor substrate for all of the transistors to be formed in the integrated circuit;
• forming a gate oxide layer in the well regions for all of the transistors to be formed in the integrated circuit;
• forming gates for all of the transistors to be formed in the integrated circuit over the gate oxide layer;
• implanting a dopant to form lightly-doped-drain regions for all of the transistors to be formed in the integrated circuit, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions where drains of the high-voltage transistors are to be formed;
• forming gate spacers at sides of the gates of all of the transistors to be formed in the integrated circuit;
• and
• implanting a dopant to form sources and drains for all of the transistors to be formed in the integrated circuit, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.