Merged gate for vertical transistors
AssigneeInternational Business Machines Corporation
InventorsBrent A. Anderson, Fee Li Lie, Edward J. Nowak, Junli Wang
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Abstract
Embodiments of the present invention are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming an insulating fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate.
Claims15
A method of forming a gate of a semiconductor device, the method comprising:
- forming a fin structure having a sidewall;
- forming an initial gate structure adjacent the sidewall;
- forming a spacer structure adjacent the sidewall and over a first region of the initial gate structure;
- and
- removing a second region of the initial gate structure, wherein the second region is not under the spacer structure.
A method of forming a semiconductor device structure, the method comprising:
- forming a first fin structure having a first sidewall;
- forming a second fin structure having a second sidewall;
- forming an initial merged gate structure adjacent the first sidewall and the second sidewall;
- wherein the initial merged gate structure comprises a merged gate region between the first fin structure and the second fin structure;
- wherein a top surface of the initial merged gate structure is below a top surface of the first fin structure and a top surface of the second fin structure;
- depositing an initial spacer structure conformally over the top surface of the first fin structure, a portion of the first sidewall, the top surface of the second fin structure, a portion of the second sidewall, and the top surface of the initial gate structure;
- and
- forming a protective structure over a portion of the initial spacer structure that is over the merged gate region.
Dependencies are inferred from the claim text.