Semiconductor packaging structure and semiconductor power device thereof

semiconductor power device comprising:

• a phase pin;
• a common substrate disposed n the phase pin, which includes a first region and a second region;
• a common conductive region disposed on the common substrate and at a location where the first region and the second region connected with each other;
• a first N type epitaxial layer disposed on the first region of the common substrate;
• a first N-type layer disposed on the first N-type epitaxial layer;
• a bus pin disposed on the first N-type layer and electrically coupled to the first N-type layer;
• a first P-type region disposed on the first N-type epitaxial layer and electrically coupled to the common conductive region;
• a second N-type epitaxial layer disposed on the second region of the common substrate;
• a second N-type layer disposed on the second N-type epitaxial layer and electrically coupled to the common conductive region;
• a second P-type region disposed on the second N-type epitaxial layer;
• and
• ground pin disposed on the second P-type region and electrically coupled to the second P-type region.