Semiconductor device and fabrication method thereof
AssigneeMagnaChip Semiconductor, Ltd.
InventorsMin Gyu Lim, Jung Hwan Lee, Yi Sun Chung
Life of this patent
Estimating the term…
Abstract
A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region.
Claims18
A semiconductor device, comprising:
- a lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) device formed in a first region of the semiconductor device;
- and
- a complementary MOS (CMOS) device formed in a second region of the semiconductor device,
- wherein the LDMOS device comprises:
- a P type well region and an N type well region formed in a substrate;
- a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region;
- a gate electrode formed on the gate insulating layer;
- a P type well pick-up region formed in the P type well region;
- a drain region formed in the N type well region;
- and
- a field relief oxide layer formed in the N type well region between the gate electrode and the drain region,
- wherein the P type well region of the LDMOS device and a P type well region of the CMOS device have substantially the same depth, and the N type well region of the LDMOS device and an N type well region of the CMOS device have substantially the same depth.
A lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) device, comprising:
- a P type well region and an N type well region thereby forming a PN junction region in a substrate;
- a source region formed in the P type well region;
- a drain region formed in the N type well region;
- a thin gate insulating layer, a thick gate insulating layer, and a relief oxide layer formed between the source region and the drain region;
- a gate electrode formed on the thin gate insulating layer, the thick gate insulating layer, and the relief oxide layer;
- and,
- a P type well pick-up region formed in the P type well region,
- wherein the gate electrode is in direct contact with the thin gate insulating layer, the thick gate insulating layer, and the relief oxide layer;
- and,
- wherein a top surface of the thick gate insulating layer is coplanar with a top surface of the relief oxide layer.
Dependencies are inferred from the claim text.