Reduced gate charge field-effect transistor
AssigneeInfineon Technologies Austria AG
InventorsDavid Laforet, Li Juin Yip, Cedric Ouvrard
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Abstract
In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region, and source diffusions formed in the body. The source diffusions are adjacent a gate trench extending through the body into the drift region and having a dielectric liner and a gate electrode situated therein. The dielectric liner includes an upper segment and a lower segment, the upper segment extending to at least a depth of the source diffusions and being significantly thicker than the lower segment.
Claims14
A method for fabricating a reduced gate charge field-effect transistor (FET), said method comprising:
- forming a drift region over a drain, and a gate trench extending into said drift region, said gate trench having a dielectric liner and a gate electrode situated therein;
- removing a portion of said gate electrode to a predetermined depth within said gate trench;
- increasing an upper thickness of said dielectric liner such that said dielectric liner comprises an upper segment and a lower segment, said upper segment extending to said predetermined depth and being significantly thicker than said lower segment;
- at least partially filling said gate trench with a conductive material to extend said gate electrode to said upper segment of said dielectric liner.
Dependencies are inferred from the claim text.