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US 9,755,059 B2Granted
Cascode structures with GaN cap layers
AssigneeCree, Inc.
InventorSaptharishi Sriram
Life of this patent
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Abstract
A transistor device including a cap layer is described. One embodiment of such a device includes cap layer between a gate and a semiconductor layer. In one embodiment, the thickness of the cap layer is between 5 nm and 100 nm. In another embodiment, the cap layer can be doped, such as delta-doped or doped in a region remote from the semiconductor layer. Devices according to the present invention can show capacitances which are less drain bias dependent, resulting in improved linearity.
Claims28
A multi-gate transistor, comprising:
- a plurality of active semiconductor layers on a substrate;
- a source and a drain in contact with at least one of said plurality of active semiconductor layers;
- a first gate between said source and drain;
- a second gate between said first gate and said drain;
- and
- a cap layer between and contacting said second gate and said plurality of active semiconductor layers, wherein said cap layer comprises a semiconductor material, wherein said first gate contacts at least one active semiconductor layer in said plurality of active semiconductor layers and said second gate is separated from said plurality of active semiconductor layers by said cap layer.
3 more elements
A cascode structure, comprising:
- a first stage comprising a first gate;
- a second stage comprising a second gate;
- a plurality of active semiconductor layers;
- wherein said second gate is separated from at least some of said plurality of active semiconductor layers by a cap layer, wherein said cap layer comprises gallium nitride (GaN);
- wherein said cap layer is shaped to define an aperture;
- and
- wherein at least a portion of said first gate is within said aperture and contacting at least one active semiconductor layer in said plurality of active semiconductor layers.
4 more elements
An integrated circuit comprising a transistor, said transistor comprising:
- a plurality of active semiconductor layers on a substrate;
- a source and a drain on at least one of said plurality of active semiconductor layers;
- a first gate between said source and drain;
- a second gate between said first gate and said drain;
- and
- a cap layer between and contacting said second gate and said plurality of active semiconductor layers wherein said cap layer is on less than all of said plurality of active semiconductor layers between said first gate and said drain.
3 more elements
Dependencies are inferred from the claim text.