Semiconductor device

A semiconductor device comprising:

• a fin-shaped active region protruding from a substrate and extending in a first direction;
• a device isolation layer formed around the fin-shaped active region on the substrate;
• a gate extending in a second direction on the device isolation layer and on the fin-shaped active region, the gate covering a top surface and both side surfaces of the fin-shaped active region and including a first side wall having a first height from the device isolation layer;
• a gate dielectric layer interposed between the fin-shaped active region and the gate;
• a plurality of corner insulating spacers formed on the device isolation layer, each of the plurality of corner insulating spacers covering the first side wall of the gate up to a second height smaller than the first height;
• and a plurality of outer portion insulating spacers each including a first portion and a second portion, the first portion covering and contacting a portion of the first side wall of the gate that is exposed by a corresponding one of the plurality of corner insulating spacers, and each of the plurality of outer portion insulating spacers having a third height greater than the first height and extending above a top surface of the gate.

A semiconductor device comprising:

• a fin-shaped active region protruding from a substrate;
• a device isolation layer formed around the fin-shaped active region on the substrate;
• a gate covering a top surface and both side surfaces of the fin-shaped active region, the gate extending on the device isolation layer to define re-entrant corner portions at opposite sides of the fin-shaped active region, each of the re-entrant corner portions formed between the gate, the fin-shaped active region, and the device isolation layer;
• a plurality of corner insulating spacers extending along a side wall of the gate in the re-entrant corner portions, each of the plurality of corner insulating spacers covering lower portions of the side wall of the gate;
• and
• a plurality of outer portion insulating spacers each including a first portion and a second portion, the first portion covering and contacting an upper portion of the side wall of the gate and a corresponding one of the plurality of corner insulating spacers, the plurality of outer portion insulating spacers having a smaller dielectric constant than the plurality of corner insulating spacers, each of the plurality of outer portion insulating spacers extending above a top surface of the gate.