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US 9,755,047 B2Granted
Semiconductor process and semiconductor device
AssigneeUnited Microelectronics Corp.
InventorsPin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
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Abstract
A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.
Claims3
A semiconductor device, comprising:
- a silicon-phosphorus (SiP) epitaxial layer serving as a source/drain region of a diamond shape silicon fin structure;
- a first metal silicide layer over the SiP epitaxial layer;
- a second metal silicide layer over the first metal silicide layer;
- a contact plug over the second metal silicide layer;
- and
- a barrier metal layer including a first metal layer and a second metal layer on the first metal layer surrounding the contact plug,
- wherein the second metal silicide layer is formed with a metal silicidation reaction between the SiP epitaxial layer and the first metal layer of the barrier metal layer by which silicon atoms from the SiP epitaxial layer pass through the first metal silicide layer for reaction with the first metal layer and thereby contains each metal element in the first metal layer of the barrier metal layer, and comprises an amorphous metal silicide layer, and the first metal silicide layer comprises a crystalline metal silicide layer;
- wherein a thickness of the first metal silicide layer is between 5 nm and 15 nm and a thickness of the second metal silicide layer is between 30 nm and 50 nm.
5 more elements
Dependencies are inferred from the claim text.