Rectifier structures with low leakage
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKing-Yuen Wong, Chen-Ju Yu, Jiun-Lei Jerry Yu, Po-Chih Chen, Fu-Wei Yao, Fu-Chih Yang
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Abstract
An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier.
Claims20
A method comprising:
- doping a second III-V compound layer that is over a first III-V compound layer to form a negatively charged region extending to a bottom of the second III-V compound layer, wherein the negatively charged region is doped with negatively charged ions;
- forming a first electrode to contact a first portion of the first III-V compound layer;
- forming a second electrode to contact a second portion of the first III-V compound layer, wherein the first portion and the second portion of the first III-V compound layer are on opposite sides of the negatively charged region;
- forming a gate dielectric over the first portion of the second III-V compound layer;
- and
- forming a gate electrode over the gate dielectric.
A method comprising:
- forming a dielectric passivation layer over a second III-V compound layer, wherein the second III-V compound layer is over a first III-V compound layer;
- forming a patterned mask over the second III-V compound layer, wherein a first portion of the second III-V compound layer is overlapped by an opening in the patterned mask, and a second portion and a third portion of the second III-V compound layer are covered by the patterned mask;
- etching the dielectric passivation layer to form an opening;
- doping the second III-V compound layer through the opening;
- removing the patterned mask;
- forming a gate dielectric over the second III-V compound layer;
- and
- forming a gate electrode over the gate dielectric.
A method comprising:
- epitaxially growing a first III-V compound layer over a substrate;
- epitaxially growing a second III-V compound layer over the first III-V compound layer;
- forming a dielectric passivation layer over the second III-V compound layer;
- forming a patterned mask over the second III-V compound layer;
- etching the dielectric passivation layer to form an opening in the dielectric passivation layer;
- forming a negatively charged region in the second III-V compound layer, wherein the negatively charged region is overlapped by the opening;
- removing the patterned mask;
- forming a gate dielectric over the second III-V compound layer;
- and
- forming a gate electrode over the gate dielectric.
Dependencies are inferred from the claim text.