Trench gate power semiconductor field effect transistor

A trench gate IGBT structure, comprising:

• a collector electrode at a bottom,
• a heavily doped collector region of a second conductivity type, the heavily doped collector region being located on a top of the collector electrode,
• a buffer region of a first conductivity type, the buffer region being located on a top of the collector region,
• a lightly doped drift region of the first conductivity type, the lightly doped drift region being located on a top of the buffer region,
• a body region of the second conductivity type, the body region being located on a top of the drift region,
• a heavily doped diffusion region of the second conductivity type, the heavily doped diffusion region connecting the body region to an emitter electrode,
• the emitter electrode, the emitter electrode being located in a trench-shaped contact hole and also on a top of a device,
• a heavily doped polysilicon emitter region of the first conductivity type, the heavily doped polysilicon emitter region being located on a top of the body region and contacted by the emitter electrode on a side wall of the trench-shaped contact hole,
• a gate dielectric, the gate dielectric covering a surface of a side wall of the body region and forming a channel between the emitter region and the drift region,
• a gate electrode, the gate electrode being close to the gate dielectric in a gate trench, and
• an interlayer dielectric (ILD), the ILD covering an upper surface of the gate electrode and an upper surface of the emitter region.

A method for manufacturing a trench gate power MOSFET structure, comprising:

• starting with an epitaxial wafer, wherein a lightly doped epitaxial layer of a first conductivity type is located on a top of the heavily doped substrate of the first conductivity type,
• forming a body region of a second conductivity type on a top of the epitaxial layer;
• forming a heavily doped polysilicon source region of the first conductivity type on a top of the body region,
• forming the gate trench by patterning the polysilicon source region and the body region,
• forming a gate dielectric in the gate trench and on an upper surface of the polysilicon source region,
• forming a gate electrode by deposition and deep etching;
• depositing a ILD on a top of the gate electrode and on the surface of the source region;
• forming a trench-shaped contact hole by patterning the ILD and the source region;
• forming a heavily doped diffusion region of the second conductivity type at the bottom of the contact hole through ion implantation and annealing, and
• forming the source electrode on a front of the wafer and the drain electrode on a back of the wafer.

A method for manufacturing an IGBT structure, comprising:

• starting with a light doping substrate wafer of a first conductivity type;
• forming a body region of a second conductivity type on a top of the substrate;
• forming a heavily doped polysilicon emitter region of the first conductivity type on a top of the body region;
• forming a gate trench by patterning the polysilicon emitter region and the body region;
• forming a gate dielectric in the gate trench and on an upper surface of the polysilicon emitter region;
• forming a gate electrode by depositing and etching thereafter;
• depositing an ILD on a top of the gate electrode and on the surface of the emitter region;
• forming a trench-shaped contact hole by patterning the ILD and the emitter region;
• forming a heavily doped diffusion of the second conductivity type at a bottom of the contact hole through ion implantation and annealing;
• forming an emitter electrode on a front of the wafer;
• thinning down the substrate wafer on a back of the wafer;
• forming a buffer region of the first conductivity type and a heavily doped collector region of the second conductivity type on the back of the wafer;
• and
• forming a collector electrode on the back of the wafer.

A method for manufacturing an IGBT structure, comprising:

• starting with a lightly doped substrate wafer of a first conductivity type,
• forming a body region of a second conductivity type on a top of the substrate;
• forming a heavily doped polysilicon emitter region of the first conductivity type on a top of the body region,
• forming a gate trench by patterning the polysilicon emitter region and the body region,
• forming a gate dielectric in the gate trench and on an upper surface of the polysilicon emitter region,
• forming a gate electrode by deposition and then etching,
• depositing an ILD on a top of the gate electrode and on the surface of the emitter region,
• thinning down the substrate wafer on a back of the wafer,
• forming a buffer region of the first conductivity type and a heavily doped collector region of the second conductivity type on the back of the wafer,
• forming a trench-shaped contact hole by patterning the ILD and the emitter region,
• forming a heavily doped diffusion region of the second conductivity type at a bottom of the contact hole through ion implantation and annealing, and
• forming an emitter electrode on a front of the wafer and a collector electrode on the back of the wafer.