Semiconductor device having nanowire

A semiconductor device, comprising:

• a gate electrode disposed on a substrate and extended in a first direction;
• an inner spacer formed on the substrate and a first portion of a sidewall of the gate electrode;
• an outer spacer formed on a second portion of the sidewall of the gate electrode,
• wherein the second portion of the sidewall of the gate electrode surrounds the first portion of the sidewall of the gate electrode;
• a first nanowire disposed on the substrate,
• wherein the first nanowire is extended in a second direction which is different from the first direction and an end portion of the first nanowire is protruded from the inner spacer and the outer spacer;
• and
• a source/drain connected with the end portion of the first nanowire,
• wherein the inner spacer is located between the substrate and the first nanowire,
• wherein the inner spacer includes a sidewall extending in the first direction,
• wherein the outer spacer covers the sidewall of the inner spacer and is in contact with the sidewall of the inner spacer, and
• wherein the first nanowire is in contact with the outer spacer and the inner spacer.

A semiconductor device, comprising:

• a plurality of nanowires disposed on a substrate,
• wherein each of the plurality of nanowires is extended in a first direction and spaced apart from the substrate;
• a gate electrode surrounding a periphery of each of the plurality of nanowires,
• wherein the gate electrode is extended in a second direction intersecting the first direction;
• a gate spacer formed on a sidewall of the gate electrode,
• the gate spacer comprising an inner sidewall and an outer sidewall facing each other,
• wherein the inner sidewall of the gate spacer faces the sidewall of the gate electrode and an end portion of each of the plurality of nanowires is protruded from the outer sidewall of the gate spacer;
• and
• a source/drain epitaxial layer disposed on at least one side of the gate electrode,
• wherein the source/drain epitaxial layer is connected to the end portion of each of the plurality of nanowires,
• wherein the gate spacer comprises an inner spacer and an outer spacer surrounding the inner spacer in a cross-section taken along the second direction,
• wherein the inner spacer is located between the substrate and each of the plurality of nanowires,
• wherein the inner spacer includes a sidewall extending in the first direction,
• wherein the outer spacer covers the sidewall of the inner spacer and is in contact with the sidewall of the inner spacer, and
• wherein each of the plurality of nanowires is in contact with the outer spacer and the inner spacer.