Method of forming a semiconductor device and structure therefor

An MOS transistor comprising:

• a semiconductor substrate;
• a first doped region overlying the semiconductor substrate, the first doped region having a major surface;
• a second doped region extending a first distance into the first doped region;
• a third doped region extending substantially the first distance into the first doped region, the third doped region spaced apart from the second doped region;
• a first portion of the first doped region positioned between the second and third doped regions, the first portion of the first doped region abutting the second doped region and the third doped region along the first distance;
• a control electrode of the MOS transistor extending substantially from the major surface substantially the first distance into a second portion of the first doped region, the control electrode disposed adjacent to the first portion of the first doped region and between the second and third doped regions wherein the control electrode is configured to form a channel region for a current flow laterally from the second doped region through the first portion of the first doped region to the third doped region wherein the current flow in the channel region extends through the first portion of the first doped region and the channel region extends vertically the first distance through the first portion of the first doped region;
• and
• wherein the first doped region, the second doped region, and the control electrode form a three sided shape that extends into the first doped region with the second doped region forming one side of the three sided shape, the third doped region forming an opposite side of the three sided shape, the control electrode forming a connecting side of the three sided shape, and the first portion of the first doped region extending into an opening of the three sided shape wherein the opening includes a space enclosed by three sides of the three sided shape.

A method of forming an MOS transistor comprising:

• providing a first doped region having a first major surface and a second major surface that is positioned opposite to the first major surface;
• forming an opening extending a distance into the first doped region;
• forming a second doped region extending into the opening;
• forming a third doped region extending into the opening and spaced apart from the second doped region;
• and
• forming a control electrode of the MOS transistor as a fourth doped region extending into the opening and positioned between the second and third doped regions, the control electrode configured to form a channel region extending laterally between a source region and a drain region, the control electrode extending a first distance into the first doped region and abutting the channel region, the control electrode formed to have a gate length that extends substantially parallel to the first major surface and a gate width that extends substantially perpendicular to the first major surface and also extends into the first doped region adjacent to the channel region.

An MOS transistor comprising:

• a first doped region having a first major surface and a second major surface that is positioned opposite to the first major surface;
• a second doped region formed in an opening in the first doped region and extending a first distance into the first doped region between the first and second major surfaces;
• a third doped region extending substantially the first distance into the first doped region, the third doped region spaced apart from the second doped region
• a first portion of the first doped region positioned between the second and third doped regions, the first portion of the first doped region abutting the third doped region along the first distance;
• and
• a control electrode of an MOS transistor extending into the first doped region, the control electrode configured to form a channel having a channel width that extends substantially a first distance between the first and second major surfaces and a channel length that extends substantially parallel to the first major surface wherein the channel width is greater than the channel length.

An MOS transistor comprising:

• a first doped region having a first major surface and a second major surface that is positioned opposite to the first major surface;
• a second doped region extending a first distance into the first doped region between the first and second major surfaces;
• a third doped region extending substantially the first distance into the first doped region, the third doped region spaced apart from the second doped region
• a first portion of the first doped region positioned between the second and third doped regions, the first portion of the first doped region abutting the third doped region along the first distance;
• a control electrode of an MOS transistor extending into the first doped region, the control electrode configured to form a channel having a channel width that extends substantially a first distance between the first and second major surfaces and a channel length that extends substantially parallel to the first major surface wherein the channel width is greater than the channel length;
• and
• a fourth doped region extending substantially the first distance into the first doped region, the fourth doped region abutting the second doped region and disposed between the second doped region and the first portion of the first doped region, wherein the channel extends laterally from substantially along an interface of the second and fourth doped regions into the fourth doped region and extends vertically substantially the first distance along the interface of the second and fourth doped regions.

A method of forming an MOS transistor comprising:

• providing doped semiconductor material having a first major surface and having a second major surface that is positioned on an opposite side from the first major surface;
• forming a first opening in the doped semiconductor material;
• forming a first doped region in the first opening;
• forming a second opening in the doped semiconductor material;
• forming a second doped region in the second opening wherein a portion of the doped semiconductor material is disposed between the first and second doped regions;
• forming a third opening in the doped semiconductor material wherein the third opening is positioned between the first opening and the second opening;
• and
• forming a third doped region in the third opening wherein the third doped region forms a gate conductor of the MOS transistor including forming the third doped region adjacent to and spaced apart from the portion of the doped semiconductor material by an insulator, the third doped region configured to form a channel region in the portion of the doped semiconductor material wherein the channel region has a width that extends from substantially the first major surface of the doped semiconductor material a distance toward the second major surface of the doped semiconductor material.