Pixel circuit

A pixel circuit, comprising:

• a first transistor, comprising:
• a first semiconductor layer comprising a first channel region, a first source region, a first drain region, and a second drain region, wherein a first portion of the first channel region is connected to the first source region, a second portion of the first channel region is connected to the first drain region, and a third portion of the first channel region is connected to the second drain region, a channel width of the second portion of the first channel region is greater than a channel width of the third portion, and the first source region is electrically connected to a voltage supply end;
• a first gate electrode partially overlapping with the first channel region;
• and
• a first insulation layer disposed between the first gate electrode and the first channel region;
• a capacitive device having a first end electrically connected to the first gate electrode of the first transistor, and a second end electrically connected to a potential source;
• a light-emitting element;
• a second transistor, comprising:
• a second semiconductor layer comprising a second channel region, a second source region, and a third drain region, wherein the second channel region is connected between the second source region and the third drain region, the second source region is directly connected to the second drain region of the first transistor, the third drain region is electrically connected to the light-emitting element, and a channel width of the second channel region of the second semiconductor layer in the second transistor is less than a channel width of the second portion of the first channel region of the first semiconductor layer in the first transistor;
• a second gate electrode partially overlapping with the second channel region;
• and
• a second insulation layer disposed between the second gate electrode and the second channel region;
• and
• a third transistor, comprising:
• a third semiconductor layer comprising a third channel region, a third source region, and a fourth drain region, wherein the third channel region is connected between the third source region and the fourth drain region, the third source region is directly connected to the first drain region of the first transistor, the fourth drain region is electrically connected to the first end of the capacitive device, and a channel width of the third channel region of the third semiconductor layer in the third transistor is less than the channel width of the second portion of the first channel region of the first semiconductor layer in the first transistor;
• a third gate electrode partially overlapping with the third channel region;
• and
• a third insulation layer disposed between the third gate electrode and the third channel region.