Multi-tier memory stack structure containing two types of support pillar structures

A monolithic three-dimensional memory device comprising:

• a first tier structure comprising a first alternating stack of first insulating layers and first electrically conductive layers and located over a substrate;
• a second tier structure comprising a second alternating stack of second insulating layers and second electrically conductive layers and located over the first tier structure;
• a plurality of memory stack structures extending through the first tier structure and the second tier structure;
• first support pillar structures extending through the first tier structure but not through the second tier structure;
• and
• second support pillar structures extending through the first tier structure and the second tier structure,
• wherein:
• the monolithic three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
• the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
• the substrate comprises a silicon substrate;
• the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
• at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
• the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
• the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level;
• and
• the array of monolithic three-dimensional NAND strings comprises:
• a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
• and
• a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

A monolithic three-dimensional memory device comprising:

• a first tier structure comprising a first alternating stack of first insulating layers and first electrically conductive layers and located over a substrate;
• a second tier structure comprising a second alternating stack of second insulating layers and second electrically conductive layers and located over the first tier structure;
• a plurality of memory stack structures extending through the first tier structure and the second tier structure;
• first support pillar structures extending through the first tier structure but not through the second tier structure;
• and
• second support pillar structures extending through the first tier structure and the second tier structure,
• wherein:
• the first support pillar structures have respective topmost surfaces at an interface between the first tier structure and the second tier structure;
• each of the plurality of memory stack structures and the second support pillar structures includes a respective layer stack that includes a first dielectric material layer, a second dielectric material layer, and a semiconductor material layer;
• a top end of each semiconductor material layer is contacted by a bottom surface of a respective doped semiconductor material portion including electrical dopants at an atomic concentration greater than 5.0×1019/cm3;
• each first subset of the doped semiconductor material portion located over the memory stack structures is a drain region that contacts a bottom surface of a respective drain contact via structure embedded in a contact level dielectric layer;
• and
• an entire top surface of each second subset of the doped semiconductor material portions located over the second support pillar structures is contacted by a bottom surface of the contact level dielectric layer.

A monolithic three-dimensional memory device comprising:

• a first tier structure comprising a first alternating stack of first insulating layers and first electrically conductive layers and located over a substrate;
• a second tier structure comprising a second alternating stack of second insulating layers and second electrically conductive layers and located over the first tier structure;
• a plurality of memory stack structures extending through the first tier structure and the second tier structure;
• first support pillar structures extending through the first tier structure but not through the second tier structure;
• second support pillar structures extending through the first tier structure and the second tier structure;
• a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the second alternating stack laterally extends farther than any overlying electrically conductive layer within the first and second alternating stacks, wherein the terrace region includes stepped surfaces of the first and second alternating stacks that continuously extend from a bottommost layer within the first alternating stack to a topmost layer within the second alternating stack, and the first and second support pillar structures are located in the terrace region;
• and
• control gate contact via structures located within the terrace region, vertically extending at least through a dielectric material portion within the second tier structure, and contacting a respective electrically conductive layer selected from the first and second electrically conductive layers.