High-K-last manufacturing process for embedded memory with metal-oxide-nitride-oxide-silicon (MONOS) memory cells

An integrated circuit (IC) comprising:

• a plurality of logic devices arranged on a logic region of a semiconductor substrate, wherein the logic devices comprise respective dielectric regions and respective logic gates arranged over the respective dielectric regions, and wherein heights of the dielectric regions vary between the dielectric regions;
• a memory cell arranged on a memory region of the semiconductor substrate, laterally adjacent to the logic region, wherein the memory cell comprises a control gate and a select gate laterally adjacent to one another, and wherein the memory cell further comprises a charge trapping layer underlying the control gate;
• an interlayer dielectric (ILD) layer arranged laterally between the control, select, and logic gates, and comprising an upper surface substantially coplanar with upper surfaces of the control, select, and logic gates;
• and
• a plurality of high κ dielectric layers comprising a first high κ dielectric layer and a second high κ dielectric layer, wherein the first high κ dielectric layer is directly under a logic gate of the logic devices and laterally contacts opposite sidewalls of the logic gate, wherein the second high κ dielectric layer is directly under the select gate and laterally contacts opposite sidewalls of the select gate, wherein a bottom surface of the second high κ dielectric layer is vertically spaced from a bottom surface of the first high κ dielectric layer, wherein the high κ dielectric layers further comprise a third high κ dielectric layer lining the control gate and covering the charge trapping layer, wherein inner sidewalls of the third high κ dielectric layer respectively contact outer sidewalls of the control gate, and wherein outer sidewalls of the third high κ dielectric layer are respectively even with outer sidewalls of the charge trapping layer;
• wherein the logic gates, the control gate, and the select gate are metal and arranged respectively within the high κ dielectric layers.

An integrated circuit (IC) comprising:

• a semiconductor substrate comprising a common source/drain region;
• a control gate dielectric region and a select gate dielectric region arranged over the semiconductor substrate, wherein the control gate dielectric region comprises a charge trapping layer and a first high κ dielectric layer, wherein the select gate dielectric region comprises a second high κ dielectric layer, wherein a bottom surface of the second high κ dielectric layer is spaced between a top surface of the semiconductor substrate and a bottom surface of the first high κ dielectric layer, and wherein the control and select gate dielectric regions have respective sidewalls that respectively adjoin opposite sides of the common source/drain region;
• a select gate electrode, a control gate electrode, and a logic gate electrode laterally spaced over the semiconductor substrate, wherein the control gate electrode is directly over and within the first high κ dielectric layer, wherein the control gate electrode has outer sidewalls respectively and laterally contacting inner sidewalls of the first high κ dielectric layer that are on opposite sides of the first high κ dielectric layer, wherein the select gate electrode is directly over and laterally contacts opposing sidewalls of the second high κ dielectric layer, wherein bottom surfaces respectively of the select, control, and logic gate electrodes are uneven, wherein top surfaces respectively of the select, control, and logic gate electrodes are even, and wherein the select and control gate electrodes are respectively arranged directly over the select and control gate dielectric regions;
• a dielectric layer arranged laterally between the select, control, and logic gate electrodes, and independent of the control and select gate dielectric regions, wherein the dielectric layer has a top surface that is even with the top surfaces respectively of the select, control, and logic gate electrodes;
• and
• a third high κ dielectric layer within which the logic gate electrode is arranged;
• wherein the first high κ dielectric layer lines the control gate electrode and covers the charge trapping layer, wherein outer sidewalls of the first high κ dielectric layer are respectively even with outer sidewalls of the charge trapping layer, wherein the first high κ dielectric layer has a U-shaped profile directly under the control gate electrode and directly over the charge trapping layer, and wherein the U-shaped profile has inner sidewalls contacting the control gate electrode and outer sidewalls even with the outer sidewalls of the charge trapping layer.