Floating gate memory cells in vertical memory
AssigneeMicron Technology, Inc.
InventorsCharles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
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Abstract
Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
Claims19
An apparatus including a vertical string of memory cells, wherein a memory cell of the vertical string of memory cells comprises:
- a control gate between a first tier of dielectric material and a second tier of dielectric material;
- a floating gate between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate contacts the first tier of dielectric material and the second tier of dielectric material;
- and
- a charge blocking structure between the floating gate and the control gate, wherein the charge blocking structure comprises a barrier film, wherein a substantially vertical portion of the barrier film is between the control gate and the floating gate, wherein a first substantially horizontal portion of the barrier film laterally extends partially between the first tier of dielectric material and the floating gate, and wherein a second substantially horizontal portion of the barrier film laterally extends partially between the second tier of dielectric material and the floating gate.
Dependencies are inferred from the claim text.