Semiconductor device with a memory device and a high-K metal gate transistor

A method of manufacturing a semiconductor device, comprising:

• forming an isolation structure in a semiconductor layer to separate a first area of said semiconductor layer from a second area of said semiconductor layer;
• forming a protection layer over said isolation structure;
• forming a memory device in and over said first area, comprising:
• forming a floating gate layer over said first area;
• forming a control gate layer over said floating gate layer formed over said first area;
• forming a select gate layer and an erase gate layer over said first area;
• and
• patterning said floating gate layer, said control gate layer, said select gate layer, and said erase gate layer to form a floating gate, control gate, select gate, and erase gate, respectively, wherein forming said protection layer comprises forming said control gate layer over said isolation structure;
• removing said protection layer after patterning said floating gate layer, said control gate layer, said select gate layer, and said erase gate layer;
• and
• forming a field effect transistor (FET) in and over said second area after said removal of said protection layer, comprising forming a gate dielectric over said second area and forming a transistor gate over said gate dielectric.

A method of manufacturing a semiconductor device, comprising:

• providing a semiconductor layer comprising a first area and a second area separated from said first area by an isolation structure;
• forming a protection layer above said isolation structure and said first and second areas;
• removing said protection layer from above said first area;
• at least partially forming a memory device in and on said first area after removing said protection layer from above said first area, wherein said protection layer remains in place above said isolation structure and said second area during a patterning of at least one of a control gate or a floating gate of said memory device;
• removing said protection layer from above said isolation structure and said second area after said patterning of said at least one of said control gate or said floating gate;
• and
• forming a field effect transistor (FET) in and over said second area after said removal of said protection layer from above said second area, wherein forming said FET comprises forming a FET gate and wherein forming said memory device comprises forming a select gate and wherein at least a part of said FET gate and said select gate are patterned from a gate layer in a same patterning process after removal of said protection layer.