Non-volatile memory device employing a deep trench capacitor

A semiconductor structure comprising:

• a power supply having a positive power supply voltage and a negative power supply voltage, the positive power supply voltage being distinct from the negative power supply voltage;
• a ground, the ground being distinct from each of the positive power supply voltage and the negative power supply voltage;
• a trench capacitor including an outer metallic layer, a node dielectric layer, and an inner metallic layer and located within a semiconductor substrate;
• and
• a set of switching devices comprising a first switching device, a second switching device and a third switching device, the set of switching devices being configured to provide a selected state from among three states based on a set of input signals;
• wherein a source node of said first switching transistor is electrically connected to said inner metallic layer and a drain node of said first switching transistor is electrically connected to:
• (a) a first node of said second switching transistor, a second node of said second switching transistor connected to said positive power supply voltage;
• and (b) to a first node of said third switching transistor, a second node of said third switching transistor connected to said negative power supply voltage;
• wherein said first, second and third switching devices are configured to controllably provide a first state in which said inner metallic layer is electrically connected to said positive power supply voltage through said first and second switching devices being turned on and said third switching device being turned off to program the node dielectric layer into a low leakage current state;
• wherein said first, second and third switching devices are configured to controllably provide a second state in which said inner metallic layer is electrically connected to said negative power supply voltage through said first and third switching devices being turned on and said second switching device being turned off to program the node dielectric layer into a high leakage current state, the difference between the low and high leakage current states being at least 5 orders of magnitude;
• and
• wherein said first, second and third switching devices are configured to controllably provide a third state in which said inner metallic layer is electrically isolated from any node having said positive power supply voltage and from any node having said negative power supply voltage by said first switching device being turned off.