US 9,754,940 B2 · Self-aligned contact metallization for reduced contact resistance

Abstract

Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g., <0.5 eV) and/or otherwise be doped to provide desired conductivity, and the p-type germanium layer can be doped, for example, with boron. After deposition of the III-V material over both the n-type source/drain regions and the germanium covered p-type source/drain regions, an etch-back process can be performed to take advantage of the height differential between n and p type regions to self-align contact types and expose the p-type germanium over p-type regions and thin the n-type III-V material over the n-type regions. The techniques can be used on planar and non-planar transistor architectures.

Claims20

Dependent claims

An integrated circuit, comprising:

a p-type germanium layer directly on at least a portion of a p-type source region and a p-type drain region;
and
an n-type III-V semiconductor material layer directly on at least a portion of an n-type source region and an n-type drain region.

Dependencies are inferred from the claim text.

Facts

Application

14/981,206Filed 28 Dec 2015 · continuation

Priority

15 Jun 2015

Published

US 2016/0118384 A128 Apr 2016

Granted

5 Sep 2017

Term ends

Not estimatedThe source records don’t support an estimate.

Classification37 codes

H10D 84/856
Complementary IGFETs, e.g. CMOS: the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/501
Field-effect transistors [FET]: fETs having stacked nanowire, nanosheet or nanoribbon channels
H10D 30/6219
Fin field-effect transistors [FinFET]: characterised by the source or drain electrodes

Family

PCT/US2011/066134Parent of this continuation · filed 20 Dec 2011

Application14/739,994Parent of this continuation · filed 15 Jun 2015

US 9,059,024 B2Parent of this continuation · filed 16 Jun 2015

US 2016/0118384 A1Pre-grant publication · published 28 Apr 2016

US 9,224,735 B2Parent of this continuation

Application13/976,075Parent of this continuation

US 2013/0277752 A1Published application

US 2015/0311204 A1Published application

US 9,754,940 B2This patent

From the US filing history. Foreign family members aren’t listed.

Self-aligned contact metallization for reduced contact resistance

Life of this patent

Self-aligned contact metallization for reduced contact resistance

Life of this patent

Abstract

Claims20