Integrated circuits having multiple gate devices with dual threshold voltages and methods for fabricating such integrated circuits

A method for fabricating an integrated circuit having a finFET with dual threshold voltages, the method comprising:

• etching a first trench and a second trench into a semiconductor substrate, wherein a semiconductor fin structure is defined from a portion of the semiconductor substrate between a first interface with the first trench and a second interface with the second trench;
• forming a first doped region in the semiconductor substrate adjacent the first interface;
• forming a first gate structure over the first doped region, wherein a first gate is defined by the first doped region and the first gate structure, and wherein the first gate is configured to operate with a first threshold voltage;
• forming a second doped region in the semiconductor substrate adjacent the second interface;
• and
• forming a second gate structure over the second doped region, wherein a second gate is defined by the second doped region and the second gate structure, and wherein the second gate is configured to operate with a second threshold voltage different from the first threshold voltage.

An integrated circuit comprising:

• a semiconductor fin structure overlying a semiconductor substrate and having a first sidewall, a second sidewall opposite the first sidewall, and an upper surface, wherein the semiconductor fin structure consists of a semiconductor material that contacts and forms the first sidewall and the second sidewall;
• a gate structure overlying the first sidewall and the second sidewall;
• a first gate defined along the first sidewall of the semiconductor fin structure;
• and
• a second gate defined along the second sidewall of the semiconductor fin structure;
• wherein the integrated circuit is configured to operate with a first threshold voltage across the first gate and to operate with a second threshold voltage across the second gate different from the first threshold voltage.