Raised metal semiconductor alloy for self-aligned middle-of-line contact

A semiconductor structure comprising:

• a plurality of functional gate structures located over at least one active region of a substrate, each of the plurality of functional gate structures comprises a stack of a gate dielectric, a gate electrode, and a gate cap;
• a plurality of planar source/drain regions, each of the plurality of planar source/drain regions positioned in a portion of the at least one active region located between adjacent functional gate structures of the plurality of functional gate structures;
• a plurality of raised source/drain regions, each of the plurality of raised source/drain regions overlying a corresponding planar source/drain region of the plurality of planar source/drain regions and having a top surface located below a top surface of the gate electrode;
• a plurality of metal semiconductor alloy regions, each of the plurality of metal semiconductor alloy regions overlying a corresponding raised source/drain region of the plurality of raised source/drain regions and having a top surface substantially coplanar with topmost surfaces of the plurality of functional gate structures;
• and
• interlevel dielectric (ILD) layer portions located on the substrate and laterally surrounding the plurality of raised source/drain regions and lower portions of the plurality of metal semiconductor alloy regions, wherein top surfaces of the ILD layer portions are located below the top surface of each of the plurality of metal semiconductor alloy regions.